View ADV7310_263510.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Multiformat 216 MHz Video Encoder with Six NSVTM 12-Bit DACs ADV7310/ADV7311
FEATURES High Definition Input Formats 8-/10-, 16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb Compliant with: SMPTE 293M (525p) BTA T-1004 EDTV2 (525p) ITU-R BT.1358 (625p/525p) ITU-R BT.1362 (625p/525p) SMPTE 274M (1080i) at 30 Hz and 25 Hz SMPTE 296M (720p) RGB in 3 10-Bit 4:4:4 Input Format HDTV RGB Supported: RGB, RGBHV Other High Definition Formats Using Async Timing Mode High Definition Output Formats YPrPb Progressive Scan (EIA-770.1, EIA-770.2) YPrPb HDTV (EIA 770.3) RGB, RGBHV CGMS-A (720p/1080i) Macrovision Rev 1.1 (525p/625p)* CGMS-A (525p) Standard Definition Input Formats CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input Standard Definition Output Formats Composite NTSC M/N Composite PAL M/N/B/D/G/H/I, PAL-60 SMPTE 170M NTSC Compatible Composite Video ITU-R BT.470 PAL Compatible Composite Video S-Video (Y/C) EuroScart RGB Component YPrPb (Betacam, MII, SMPTE/EBU N10) Macrovision Rev 7.1.L1* CGMS/WSS Closed Captioning GENERAL FEATURES Simultaneous SD and HD Inputs and Outputs Oversampling up to 216 MHz Programmable DAC Gain Control Sync Outputs in All Modes On-Board Voltage Reference Six 12-Bit NSV Precision Video DACs 2-Wire Serial I2C (R) Interface Dual I/O Supply 2.5 V/3.3 V Operation Analog and Digital Supply 2.5 V On-Board PLL 64-Lead LQFP Package Lead (Pb) Free Product APPLICATIONS High End DVD High End PS DVD Recorders/Players SD/Prog Scan/HDTV Display Devices SD/HDTV Set Top Boxes Professional Video Systems
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
STANDARD DEFINITION CONTROL BLOCK COLOR CONTROL BRIGHTNESS DNR GAMMA PROGRAMMABLE FILTERS SD TEST PATTERN D E M U X
ADV7310/ ADV7311
12-BIT DAC O V E R S A M P L I N G 12-BIT DAC 12-BIT DAC 12-BIT DAC 12-BIT DAC 12-BIT DAC
Y9-Y0 C9-C0 S9-S0
PROGRAMMABLE RGB MATRIX
HIGH DEFINITION CONTROL BLOCK HD TEST PATTERN HSYNC VSYNC BLANK CLKIN_A CLKIN_B TIMING GENERATOR COLOR CONTROL ADAPTIVE FILTER CTRL SHARPNESS FILTER
PLL
I2C INTERFACE
GENERAL DESCRIPTION
The ADV(R)7310/ADV7311 is a high speed, digital-to-analog encoder on a single monolithic chip. It includes six high speed NSV video D/A converters with TTL compatible inputs. The ADV7310/ADV7311 has separate 8-/10-/16-/20-bit input ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical, and blanking signals or EAV/SAV timing codes control the insertion of appropriate synchronization signals into the digital data stream and therefore the output signal.
Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. *ADV7310 Only
2
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADV7310/ADV7311
DETAILED FEATURES High Definition Programmable Features (720p 1080i) 2 Oversampling (148.5 MHz) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Field/Frame) Fully Programmable YCrCb to RGB Matrix Gamma Correction Programmable Adaptive Filter Control Programmable Sharpness Filter Control CGMS-A (720p/1080i) High Definition Programmable Features (525p/625p) 8 Oversampling (216 MHz Output) Internal Test Pattern Generator (Color Hatch, Black Bar, Flat Frame) Individual Y and PrPb Output Delay Gamma Correction Programmable Adaptive Filter Control Fully Programmable YCrCb to RGB Matrix Undershoot Limiter Macrovision Rev 1.1 (525p/625p)* CGMS-A (525p) Standard Definition Programmable Features 16 Oversampling (216 MHz) Internal Test Pattern Generator (Color Bars, Black Bar) Controlled Edge Rates for Sync, Active Video Individual Y and PrPb Output Delay Gamma Correction Digital Noise Reduction (DNR) Multiple Chroma and Luma Filters Luma-SSAFTM Filter with Programmable Gain/Attenuation PrPb SSAFTM Separate Pedestal Control on Component and Composite/S-Video Output VCR FF/RW Sync Mode Macrovision Rev 7.1.L1* CGMS/WSS Closed Captioning Standards Directly Supported
Resolution 720 720 720 720 720 1280 1920 1920 480 576 483 480 576 720 1080 1080
Frame Rate (Hz) 29.97 25 59.94 59.94 50 60 30 25
Clk Input (MHz) 27 27 27 27 27 74.25 74.25 74.25
Standard ITU-R BT.656 ITU-R BT.656 SMPTE 293M BTA T-1004 ITU-R BT.1362 SMPTE 296M SMPTE 274M SMPTE 274M*
Other standards are supported in Async Timing Mode. *SMPTE 274M-1998: System no. 6
DETAILED FUNCTIONAL BLOCK DIAGRAM
HD PIXEL INPUT
CLKIN_B
Y DEINTER- CR LEAVE CB
TEST PATTERN
SHARPNESS AND ADAPTIVE FILTER CONTROL
Y COLOR CR COLOR CB COLOR
4:2:2 TO 4:4:4
PS 8 HDTV 2
DAC
DAC P_HSYNC P_VSYNC P_BLANK TIMING GENERATOR
CLOCK CONTROL AND PLL U UV SSAF RGB MATRIX SD 16
DAC
S_HSYNC S_VSYNC S_BLANK CLKIN_A CB DEINTER- CR LEAVE Y
TIMING GENERATOR
V
DAC
DAC TEST PATTERN DNR GAMMA COLOR CONTROL SYNC INSERTION LUMA AND CHROMA FILTERS
SD PIXEL INPUT
2 OVERSAMPLING
FSC MODULATION
CGMS WSS
DAC
TERMINOLOGY
HDTV YCrCb YPrPb
SD HD PS
Standard Definition Video, conforming to ITU-R BT.601/ITU-R BT.656. High Definition Video, i.e., Progressive Scan or HDTV. Progressive Scan Video, conforming to SMPTE 293M, ITU-R BT.1358, BTAT-1004EDTV2, or BTA1362.
High Definition Television Video, conforming to SMPTE 274M or SMPTE 296M. SD, PS, or HD Component Digital Video. SD, PS, or HD Component Analog Video.
*ADV7310 Only
-2-
REV. A
ADV7310/ADV7311
CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2 TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . 14 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15 MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 16 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Subaddress Register (SR7-SR0) . . . . . . . . . . . . . . . . . . . 17 INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 30 Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 30 Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 30 Simultaneous Standard Definition and Progressive Scan or HDTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Progressive Scan at 27 MHz (Dual Edge) or 54 MHz . . . 31 OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 33 TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 34 HD TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SD Real-Time Control, Subcarrier Reset, and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 38 Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . . 38 Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 40 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 41 COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 45 HD Y Level, HD Cr Level, HD Cb Level . . . . . . . . . . . . 45 HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 45 SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 45 SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . HD Sharpness Filter Mode . . . . . . . . . . . . . . . . . . . . . . . HD Adaptive Filter Mode . . . . . . . . . . . . . . . . . . . . . . . . HD Sharpness Filter and Adaptive Filter Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD Digital Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . BOARD DESIGN AND LAYOUT CONSIDERATIONS . DAC Termination and Layout Considerations . . . . . . . . Video Output Buffer and Optional Output Filter . . . . . . . PCB Board Layout Considerations . . . . . . . . . . . . . . . . . Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 1--COPY GENERATION MANAGEMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PS CGMS Data Registers 2-0 . . . . . . . . . . . . . . . . . . . . . SD CGMS Data Registers 2-0 . . . . . . . . . . . . . . . . . . . . . HD/PS CGMS [Address 12h, Bit 6] . . . . . . . . . . . . . . . . Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 2--SD WIDE SCREEN SIGNALING . . . . . . APPENDIX 3--SD CLOSED CAPTIONING . . . . . . . . . . APPENDIX 4--TEST PATTERNS . . . . . . . . . . . . . . . . . . APPENDIX 5--SD TIMING MODES . . . . . . . . . . . . . . . Mode 0 (CCIR-656)--Slave Option . . . . . . . . . . . . . . . . Mode 0 (CCIR-656)--Master Option . . . . . . . . . . . . . . . Mode 1--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3--Master/Slave Option . . . . . . . . . . . . . . . . . . . . . APPENDIX 6--HD TIMING . . . . . . . . . . . . . . . . . . . . . . APPENDIX 7--VIDEO OUTPUT LEVELS . . . . . . . . . . . HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . YUV Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX 8--VIDEO STANDARDS . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 48 49 49 49 50 52 53 53 53 53 53 53 53 53 54 54 55 55 55 57 57 57 57 59 59 59 59 59 59 61 62 63 66 66 67 68 69 70 71 72 73 74 74 75 76 80 82 83
REV. A
-3-
2.375 ADV7310/ADV7311-SPECIFICATIONS (V T= 2.375 V-2.625toV,70V C),= unlessV-2.625 V; noted.) = 2.375-3.6 V, V = 1.235 V, R = 3040 , R = 300 . All specifications to T (0 C otherwise V
AA DD DD_IO REF SET LOAD MIN MAX
Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity2, +ve Differential Nonlinearity2, -ve DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Three-State Leakage Current Three-State Output Capacitance DIGITAL AND CONTROL INPUTS Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current Input Capacitance, CIN ANALOG OUTPUTS Full-Scale Output Current Output Current Range DAC-to-DAC Matching Output Compliance Range, VOC Output Capacitance, COUT VOLTAGE REFERENCE Internal Reference Range, VREF External Reference Range, VREF VREF Current4 POWER REQUIREMENTS Normal Power Mode IDD5
1
Min
Typ 12 1.5 0.25 1.5
Max
Unit Bits LSB LSB LSB
Test Conditions
0.4 [0.4]3 2.4[2.0]
3
1.0 2 2 0.8 3 2 4.1 4.1 0 4.33 4.33 1.0 1.0 7 1.235 1.235 10 4.6 4.6 1.4
V V A pF V V A pF mA mA % V pF V V A
ISINK = 3.2 mA ISOURCE = 400 A VIN = 0.4 V, 2.4 V
VIN = 2.4 V
1.15 1.15
1.3 1.3
IDD_IO IAA6, 7 Sleep Mode IDD IAA IDD_IO POWER SUPPLY REJECTION RATIO
170 110 95 172 1.0 39
1908 45
mA mA mA mA mA mA A A A %/%
SD Only [16 ] PS Only [8 ] HDTV Only [2 ] SD[16 , 10-bit] + PS[8 , 20-bit]
200 10 250 0.01
NOTES 1 Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios. 2 DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for -ve DNL, the actual step value lies below the ideal step value. 3 Value in brackets for V DD_IO = 2.375 V-2.75 V. 4 External current required to overdrive internal V REF. 5 IDD, the circuit current, is the continuous current required to drive the digital core. 6 IAA is the total current required to supply all DACs including the V REF circuitry and the PLL circuitry. 7 All DACs on. 8 Guaranteed maximum by characterization. Specifications subject to change without notice.
-4-
REV. A
ADV7310/ADV7311 DYNAMIC SPECIFICATIONS
3040 , RLOAD = 300
Parameter PROGRESSIVE SCAN MODE Luma Bandwidth Chroma Bandwidth SNR HDTV MODE Luma Bandwidth Chroma Bandwidth STANDARD DEFINITION MODE Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermodulation Chroma/Luma Gain Inequality Chroma/Luma Delay Inequality Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain Differential Phase SNR
Specifications subject to change without notice.
(VAA = 2.375 V-2.625 V, VDD = 2.375 V-2.625 V; VDD_IO = 2.375 V-3.6 V, VREF = 1.235 V, RSET = . All specifications TMIN to TMAX (0 C to 70 C), unless otherwise noted.)
Min Typ 12.5 5.8 65.6 72 30 13.75 0.2 0.20 0.84 -0.2 0 96.7 -1.0 0.2 84 75.3 0.25 0.2 63.5 77.7 Max Unit MHz MHz dB dB MHz MHz
o
Test Conditions
Luma ramp unweighted Flat field full bandwidth
% % o % % ns % dB dB %
o
Referenced to 40 IRE
dB dB
NTSC NTSC Luma ramp Flat field full bandwidth
REV. A
-5-
ADV7310/ADV7311 TIMING SPECIFICATIONS
RLOAD = 300
Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 RESET Low Time ANALOG OUTPUTS Analog Output Delay2 Output Skew CLOCK CONTROL AND PIXEL PORT3 fCLK fCLK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t111 Data Hold Time, t121 SD Output Access Time, t13 SD Output Hold Time, t14 HD Output Access Time, t13 HD Output Hold Time, t14 PIPELINE DELAY4
1
(VAA = 2.375 V-2.625 V, VDD = 2.375 V-2.625 V; VDD_IO = 2.375 V-3.6 V, VREF = 1.235 V, RSET = 3040 . All specifications TMIN to TMAX (0 C to 70 C), unless otherwise noted.)
Min 0 0.6 1.3 0.6 0.6 100 Typ Max 400 Unit kHz s s s s ns ns ns s ns ns ns 27 81 40 40 2.0 2.0 15 5.0 14 5.0 63 76 35 41 36 MHz MHz % of one clk cycle % of one clk cycle ns ns ns ns ns ns clk cycles clk cycles clk cycles clk cycles clk cycles Progressive scan mode HDTV mode/async mode Test Conditions
,
First clock generated after this period relevant for repeated start condition
300 300 0.6 100 7 1
SD [2 , 16 ] SD component mode [16 ] PS [1 ] PS [8 ] HD[2 , 1 ]
NOTES 1 Guaranteed by characterization. 2 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: C[9:0]; Y[9:0], S[9:0] Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK. 4 SD, PS = 27 MHz, HD = 74.25 MHz. Specifications subject to change without notice.
-6-
REV. A
ADV7310/ADV7311
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9-C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL OUTPUTS
t13
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9-C0
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
t11
S9-S0 CONTROL OUTPUTS Cr 0 Cr1 Cr 2 Cr3
t13
Cr 4 Cr5
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]
REV. A
-7-
ADV7310/ADV7311
CLKIN_A
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
G0
G1
G2
G3
G4
G5
C9-C0
B0
B1
B2
B3
B4
B5
t11
S9-S0 CONTROL OUTPUTS R0 R1 R2 R3
t13
R4 R5
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]
CLKIN_B*
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Y9-Y0 Cb0 Y0
t10
Cr0
Y1
Crxxx
Yxxx
t12 t11
CONTROL OUTPUTS
t12 t11 t13
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
*CLKIN_B MUST BE USED IN THIS PS MODE.
Figure 4. PS 4:2:2 10-Bit Interleaved at 27 MHz HSYNC/VSYNC Input Mode [Input Mode 100]
-8-
REV. A
ADV7310/ADV7311
CLKIN_A
t9
CONTROL INPUTS P_VSYNC, P_HSYNC, P_BLANK Y9-Y0 Cb0
t10
Y0
Cr0
Y1
Crxxx
Yxxx
t11
CONTROL OUTPUTS
t12
t13 t14
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
Figure 5. PS 4:2:2 1
10-Bit Interleaved at 54 MHz HSYNC/VSYNC Input Mode [Input Mode 111]
CLKIN_B*
t9
t10
Y9-Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t12 t11
CONTROL OUTPUTS
t12 t11 t13
t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
*CLKIN_B USED IN THIS PS ONLY MODE.
Figure 6. PS Only 4:2:2 1
CLKIN_A
10-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]
t9
t10
Y9-Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t11
CONTROL OUTPUTS
t12
t13 t14
t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME
NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0
01 BIT-1
Figure 7. PS Only 4:2:2 1
10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]
REV. A
-9-
ADV7310/ADV7311
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
HD INPUT
C9-C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT
Cb0
Y0
Cr0
Y1
Cb1
Y2
t11
Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101: SD Oversampled] [Input Mode 110: HD Oversampled]
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK
t10
t12
Y9-Y0
Y0
Y1
Y2
Y3
Y4
Y5
PS INPUT
C9-C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT
Cb0
Y0
Cr0
Y1
Cb1
Y2
t11
Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]
-10-
REV. A
ADV7310/ADV7311
CLKIN_B
t9
CONTROL INPUTS P_HSYNC, P_VSYNC, P_BLANK Cb0 Y0
t10
PS INPUT Cr0 Y1 Crxxx Yxxx
Y9-Y0
t11
t12 t11
t12
CLKIN_A
CONTROL INPUTS
S_HSYNC, S_VSYNC, S_BLANK S9-S0
t9
t10
t12
SD INPUT Cb0 Y0 Cr0 Y1 Cb1 Y2
t11
Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]
CLKIN_A
t9
CONTROL INPUTS S_HSYNC, S_VSYNC, S_BLANK
t10
t12
IN SLAVE MODE
S9-S0/Y9-Y0*
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]
REV. A
-11-
ADV7310/ADV7311
CLKIN_A
t9
CONTROL INPUTS S_HSYNC, S_VSYNC, S_BLANK S9-S0/Y9-Y0*
t10
t12
IN SLAVE MODE
Y0
Y1
Y2
Y3
C9-C0
Cb0
Cr0
Cb2
Cr2
t11
CONTROL OUTPUTS
t13
IN MASTER/SLAVE MODE
t14
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]
P_HSYNC
P_VSYNC
a P_BLANK
Y9-Y0
Y0
Y1
Y2
Y3
C9-C0
Cb0
Cr0
Cr1
Cb1
b a = 16 CLKCYCLES FOR 525p a = 12 CLKCYCLES FOR 626p a = 44 CLKCYCLES FOR 1080i @ 30Hz, 25Hz a = 70 CLKCYCLES FOR 720p AS RECOMMENDED BY STANDARD b(MIN) = 122 CLKCYCLES FOR 525p b(MIN) = 132 CLKCYCLES FOR 625p b(MIN) = 236 CLKCYCLES FOR 1080i @ 30Hz, 25Hz b(MIN) = 300 CLKCYCLES FOR 720p
Figure 13. HD 4:2:2 Input Timing Diagram
-12-
REV. A
ADV7310/ADV7311
P_HSYNC
P_VSYNC
a P_BLANK
Y9-Y0
Cb
Y
Cr
Y
b a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p
Figure 14. PS 4:2:2 1
10-Bit Interleaved Input Timing Diagram
S_HSYNC
S_VSYNC
PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES
S_BLANK
S9-S0/Y9-Y0*
Cb
Y
Cr
Y
*SELECTED BY ADDRESS 0x01 BIT 7
PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES
Figure 15. SD Timing Input for Timing Mode 1
t3
SDA
t5
t3
t6
SCLK
t1
t2
t7
t4
t8
Figure 16. MPU Port Timing Diagram
REV. A
-13-
ADV7310/ADV7311
ABSOLUTE MAXIMUM RATINGS*
VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to -0.3 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to -0.3 V VDD_IO to IO_GND . . . . . . . . . . . . -0.3 V to VDD_IO to +0.3 V Ambient Operating Temperature (TA) . . . . . . . . . 0C to 70C Storage Temperature (TS) . . . . . . . . . . . . . . . -65C to +150C Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The ADV7310/ADV7311 is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255C ( 5C). In addition it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220C to 235C.
ORDERING GUIDE*
THERMAL CHARACTERISTICS
JC = 11C/W JA = 47C/W
Model
Package Description
Package Option ST-64 ST-64
ADV7310KST Plastic Quad Flat Package ADV7311KST Plastic Quad Flat Package EVAL-ADV7310EB Evaluation Board EVAL-ADV7311EB Evaluation Board
*Analog output short circuit to any power supply or common can be of an indefinite duration.
PIN CONFIGURATION
S_HSYNC RTC_SCR_TR CLKIN_B GND_IO S_VSYNC
48 S_BLANK PIN 1 IDENTIFIER 47 RSET1 46 VREF 45 COMP1 44 DAC A 43 DAC B 42 DAC C 41 VAA 40 AGND 39 DAC D 38 DAC E 37 DAC F 36 COMP2 35 RSET2 34 EXT_LF 33 RESET 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DGND
VDD
S4
S3
S2
S1
S9
S8
S7
S6
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_IO 1 Y0 2 Y1 3 Y2 4 Y3 5 Y4 6 Y5 7 Y6 8 Y7 9 VDD 10 DGND 11 Y8 12 Y9 13 C0 14 C1 15 C2 16
ADV7310/ADV7311
TOP VIEW (Not to Scale)
S5
S0 C9
P_VSYNC P_BLANK
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7310/ADV7311 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
P_HSYNC
-14-
CLKIN_A
I2C ALSB
SCLK
C3
SDA
C5
C6
C7
C8
C4
REV. A
ADV7310/ADV7311
PIN FUNCTION DESCRIPTIONS
Mnemonic DGND AGND CLKIN_A CLKIN_B COMP1,2 DAC A DAC B DAC C DAC D DAC E DAC F P_HSYNC P_VSYNC P_BLANK S_BLANK S_HSYNC S_VSYNC Y9-Y0 C9-C0 S9-S0 RESET RSET1,2 SCLK SDA ALSB VDD_IO VDD VAA VREF EXT_LF IC GND_IO
2
Input/Output G G I I O O O O O O O I I I I/O I/O I/O I I I I I I I/O I P P P I/O I I
Function Digital Ground. Analog Ground. Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes. Compensation Pin for DACs. Connect 0.1 F capacitor from COMP pin to VAA. CVBS/Green/Y/Y Analog Output. Chroma/Blue/U/Pb Analog Output. Luma/Red/V/Pr Analog Output. In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Y/Green [HD] Analog Output. In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pr/Red Analog Output. In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD Mode: Pb/Blue [HD] Analog Output. Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode. Video Blanking Control Signal for SD Only. Video Horizontal Sync Control Signal for SD Only. Video Vertical Sync Control Signal for SD Only. SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2. Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data. The LSB is set up on pin C0. For 8-bit data input, LSB is set up on C2. SD or Progressive Scan/HDTV Input Port for Cr[Red/V] data in 4:4:4 input mode. LSB is set up on pin S0. For 8-bit data input, LSB is set up on S2. This input resets the on-chip timing generator and sets the ADV7310/ADV7311 into default register setting. RESET is an active low signal. A 3040 resistor must be connected from this pin to AGND and is used to control the amplitudes of the DAC outputs. I2C Port Serial Interface Clock Input. I2C Port Serial Data Input/Output. TTL Address Input. This signal sets up the LSB of the I2C address. When this pin is tied low, the I2C filter is activated, which reduces noise on the I2C interface. Power Supply for Digital Inputs and Outputs. Digital Power Supply. Analog Power Supply. Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). External Loop Filter for the Internal PLL. Multifunctional Input. Real time control (RTC) input, timing reset input, subcarrier reset input. This input pin must be tied high (VDD_IO) for the ADV7310/ADV7311 to interface over the I2C port. Digital Input/Output Ground.
RTC_SCR_TR I
REV. A
-15-
ADV7310/ADV7311
MPU PORT DESCRIPTION
The ADV7310/ADV7311 support a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7310/ ADV7311. Each slave device is recognized by a unique address. The ADV7310/ADV7311 have four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 17. The LSB sets either a read or write operation. Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7310/ADV7311 to Logic 0 or Logic 1. When ALSB is set to 1, there is greater input bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to 0, there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X
A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral. The ADV7310/ADV7311 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. There is a subaddress auto-increment facility. This allows data to be written to or read from registers in ascending subaddress sequence starting at any valid subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then they cause an immediate jump to the idle condition. During a given SCL high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7310/ADV7311 will not issue an acknowledge and will return to the idle condition. If in auto-increment mode the user exceeds the highest subaddress, the following action will be taken: 1. In read mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge condition is when the SDA line is not pulled low on the ninth pulse. 2. In write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7310/ADV7311, and the part will return to the idle condition. Before writing to the subcarrier frequency registers, it is a requirement that the ADV7310/ADV7311 has been reset at least once after power-up. The four subcarrier frequency registers must be updated, starting with subcarrier frequency register 0 through subcarrier frequency register 3. The subcarrier frequency will not update until the last subcarrier frequency register byte has been received by the ADV7310/ADV7311. Figure 19 illustrates an example of data transfer for a write sequence and the start and stop conditions. Figure 20 shows bus write and read sequences.
Figure 17. ADV7310 Slave Address = D4h
0 1 0 1 0 1 A1 ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ X
Figure 18. ADV7311 Slave Address = 54h
To control the various devices on the bus, the following protocol must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data.
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9
1-7
8
9
P STOP
START ADRR R/W ACK
SUBADDRESS ACK
DATA
ACK
Figure 19. Bus Data Transfer
-16-
REV. A
ADV7310/ADV7311
WRITE SEQUENCE S SLAVE ADDR A(S) SUBADDR A(S) DATA A(S) LSB = 1 SUBADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P DATA A(S) P LSB = 0 READ SEQUENCE S SLAVE ADDR A(S)
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 20. Read and Write Sequence
REGISTER ACCESSES
Register Programming
The MPU can write to or read from all of the registers of the ADV7310/ADV7311 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is then performed from/to the target address, which increments to the next address until a stop command is performed on the bus.
The following tables describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated.
Subaddress Register (SR7-SR0)
The communications register is an 8-bit write only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place.
REV. A
-17-
ADV7310/ADV7311
SR7- SR0 Register
00h Power Mode Register
Bit Description
Sleep Mode. With this control enabled, the current consumption is reduced to A level. All DACs and the internal 2 PLL cct are disabled. I C registers can be read from and written to in Sleep Mode. PLL and Oversampling Control. This control allows the internal PLL cct to be powered down and the over-sampling to be switched off. DAC F: Power On/Off DAC E: Power On/Off DAC D: Power On/Off DAC C: Power On/Off DAC B: Power On/Off DAC A: Power On/Off
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 1
Register Setting
Sleep Mode off Sleep Mode on
Register Reset Values (Shaded)
FCh
0 1
PLL on PLL off
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1
DAC F off DAC F on DAC E off DAC E on DAC D off DAC D on DAC D off DAC C on DAC B off DAC B on DAC A off DAC A on Disabled Enabled Cb clocked on rising edge Y clocked on rising edge Only for PS interleaved input at 27 MHz Only for PS dual edge clk mode
01h
Mode Select Register
BTA T-1004 or BT.1362 Compatibility Clock Edge Reserved Clock Align
Only if two input clocks are used Must be set if the phase delay between the two input clocks is <9.25 ns or >27.75 ns. SD input only PS input only HDTV input only SD and PS [20-bit] SD and PS [10-bit] SD and HDTV [SD oversampled] SD and HDTV [HDTV oversampled] PS only [at 54 MHz] 10-bit data on S bus 10-bit data on Y bus SD Mode 10-bit/20-bit Modes 38h
Input Mode
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Y/S Bus Swap
0 1
-18-
REV. A
ADV7310/ADV7311
SR7- SR0
02h
Register
Mode Register 0
Bit Description
Reserved Test Pattern Black Bar
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0 1
Bit 1
0
Bit 0
0
Register Setting
Zero must be written to these bits Disabled Enabled
Reset Values
20h
0x11h, Bit 2 must also be enabled
RGB Matrix
0 1
Sync on RGB
1
0 1 0 1 0 1
Disable Programmable RGB matrix Enable Programmable RGB matrix No Sync Sync on all RGB outputs RGB component outputs YUV component outputs No Sync output Output SD Syncs on HSYNC output, VSYNC output, BLANK output No Sync output Output HD Syncs on HSYNC output, VSYNC output, BLANK output x x x x LSB for GY LSB for RV LSB for BU LSB for GV LSB for GU 03h F0h
RGB/YUV Output SD Sync
HD Sync
0 1
03h 04h
RGB Matrix 0 RGB Matrix 1 x x x x x x x x x 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 0 1 x x x x x 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 x x x x x 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 x x x x x 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 x x x x x 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 x x
05h 06h 07h 08h 09h 0Ah
RGB Matrix 2 RGB Matrix 3 RGB Matrix 4 RGB Matrix 5 RGB Matrix 6 DAC A, B, C Output Level2 Positive Gain to DAC Output Voltage
x x x x x 0 0 0 0 0 Negative Gain to DAC Output Voltage 1 1 1 1 0 0 0 0 0 Negative Gain to DAC Output Voltage 1 1 1 1
x x x x x 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1
x x x x x 0 1 0 ... 1 0 0 1 0 ... 1 0 1 0 ... 1 0 0 1 0 ... 1
Bit 9-2 for GY Bit 9-2 for GU Bit 9-2 for GV Bit 9-2 for BU Bit 9-2 for RV 0% +0.018% 0.036% ...... +7.382% +7.5% -7.5% -7.382% -7.364% ....... -0.018% 0% +0.018% 0.036% ...... +7.382% +7.5% -7.5% -7.382% -7.364% ....... -0.018%
4Eh 0Eh 24h 92h 7Ch 00h
0Bh
DAC D, E, F Output Level
Positive Gain to DAC Output Voltage
00h
0Ch 0Dh 0Eh 0Fh
Reserved Reserved Reserved Reserved
00h 00h 00h 00h
NOTES 1 For more detail, refer to Appendix 7. 2 For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.
REV. A
-19-
ADV7310/ADV7311
SR7- SR0
10h
Register
HD Mode Register 1
Bit Description
HD Output Standard
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0 0 1 1
Bit 0
0 1 0 1
Register Setting
EIA770.2 output EIA770.1 output Output levels for full input range Reserved HSYNC, VSYNC, BLANK EAV/SAV codes Async Timing Mode Reserved 525p 625p 1080i 720p BLANK active high BLANK active low Macrovision off
Reset Values
00h
HD Input Control Signals
0 0 1 1
0 1 0 1
HD 625p HD 720p HD BLANK Polarity HD Macrovision for 525p/625p 11h HD Mode Register 2 HD Pixel Data Valid 0 1 0 1 0 1
0 1
0 1 0
Macrovision on Pixel data valid off Pixel data valid on Reserved HD test pattern off HD test pattern on Hatch Field/frame Disabled Enabled Disabled -11 IRE -6 IRE -1.5 IRE Disabled
00h
HD Test Pattern Enable HD Test Pattern Hatch/Field HD VBI Open HD Undershoot Limiter 0 0 1 1 HD Sharpness Filter 12h HD Mode Register 3 HD Y Delay with Respect to Falling Edge of HSYNC 0 1 0 1 0 1 0 1 0 1
0 1
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
Enabled 0 clk cycles 1 clk cycles 2 clk cycles 3 clk cycles 4 clk cycles 0 clk cycles 1 clk cycle 2 clk cycles 3 clk cycles 4 clk cycles Disabled Enabled Disabled Enabled
HD Color Delay with Respect to Falling Edge of HSYNC
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
HD CGMS HD CGMS CRC 0 1
0 1
-20-
REV. A
ADV7310/ADV7311
SR7- SR0 Register
13h HD Mode Register 4
Bit Description
HD Cr/Cb Sequence
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 1
Register Setting
Cb after falling edge of HSYNC Cr after falling edge of HSYNC 0 must be written to this bit 8-bit input 10-bit input Disabled Enabled 0 must be written to this bit Disabled Enabled 4:4:4 4:2:2 Disabled
Reset Values
Reserved HD Input Format Sinc Filter on DAC D, E, F Reserved HD Chroma SSAF HD Chroma Input HD Double Buffering 14h HD Mode Register 5 HD Timing Reset 0 1 0 1 0 1 0 0 1 0 1
0
x
Enabled A low-high-low transition resets the internal HD timing counters 30 Hz/2200 total samples/lines 25 Hz/2640 total samples/lines 0 must be written to these bits 0 = Field Input 1 = VSYNC Input Update field/line counter Field/line counter free running 0 must be written to this bit Disabled Enabled Disabled Enabled DAC E = Pb; DAC F = Pr DAC E = Pr; DAC F = Pb Gamma Curve A Gamma Curve B Disabled Enabled Mode A Mode B Disabled Enabled
00h
1080i Frame Rate
0 0
0 1
Reserved HD VSYNC/Field Input Lines/Frame 1 0 1 15h HD Mode Register 6 Reserved HD RGB Input HD Sync on PrPb HD Color DAC Swap
0 0 1
0
0
0
0 0 1 0 1 0 1
00h
HD Gamma Curve A/B HD Gamma Curve Enable HD Adaptive Filter Mode2 HD Adaptive Filter Enable 2 0 1 0 1 0 1
0 1
NOTES 1 When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1, the field/line counters are free running and wrap around when external sync signals indicate so. 2 Adaptive Filter mode is not available in PS only @ 54 MHz input mode.
REV. A
-21-
ADV7310/ADV7311
SR7- SR0 Register
16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h HD Sharpness Filter Gain HD Y Level* HD Cr Level* HD Cb Level* Reserved Reserved Reserved Reserved Reserved Reserved Reserved HD Sharpness Filter Gain Value A 0 0 .. 0 1 .. 1 HD Sharpness Filter Gain Value B 0 0 .. 0 1 .. 1 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h HD CGMS Data 0 HD CGMS Data 1 HD CGMS Data 2 HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma A HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD Gamma B HD CGMS Data Bits HD CGMS Data Bits HD CGMS Data Bits HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve A Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points HD Gamma Curve B Data Points 0 C15 C7 x x x x x x x x x x x x x x x x x x x x 0 0 .. 1 0 .. 1 0 C14 C6 x x x x x x x x x x x x x x x x x x x x 0 0 .. 1 0 .. 1 0 C13 C5 x x x x x x x x x x x x x x x x x x x x 0 1 .. 1 0 .. 1 0 C12 C4 x x x x x x x x x x x x x x x x x x x x C19 C11 C3 x x x x x x x x x x x x x x x x x x x x C18 C10 C2 x x x x x x x x x x x x x x x x x x x x C17 C9 C1 x x x x x x x x x x x x x x x x x x x x C16 C8 C0 x x x x x x x x x x x x x x x x x x x x 0 0 .. 1 0 .. 1 0 0 .. 1 0 .. 1 0 1 .. 1 0 .. 1 Gain A = 0 Gain A = +1 ...... Gain A = +7 Gain A = -8 ...... Gain A = -1 Gain B = 0 Gain B = +1 ....... Gain B = +7 Gain B = -8 ........ Gain B = -1 CGMS 19-16 CGMS 15-8 CGMS 7-0 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
Bit Description
Bit 7
x x x
Bit 6
x x x
Bit 5
x x x
Bit 4
x x x
Bit 3
x x x
Bit 2
x x x
Bit 1
x x x
Bit 0
x x x
Register Setting
Y level value Cr level value Cb level value
Reset Values
A0h 80h 80h 00h 00h 00h 00h 00h 00h 00h 00h
NOTES Programmable gamma correction is not available in PS only @ 54 MHz input mode. *For use with internal test pattern only.
-22-
REV. A
ADV7310/ADV7311
SR7- SR0 Register
38h HD Adaptive Filter Gain 1
Bit Description
HD Adaptive Filter Gain 1 Value A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0 0 .. 0 1 .. 1
Bit 2
0 0 .. 1 0 .. 1
Bit 1
0 0 .. 1 0 .. 1
Bit 0
0 1 .. 1 0 .. 1
Register Setting
Gain A = 0 Gain A = +1 ...... Gain A = +7 Gain A = -8 ...... Gain A = -1 Gain B = 0 Gain B = +1 ....... Gain B = +7 Gain B = -8 ........ Gain B = -1
Reset Values
00h
HD Adaptive Filter Gain 1 Value B
0 0 .. 0 1 .. 1
0 0 .. 1 0 .. 1
0 0 .. 1 0 .. 1
0 1 .. 1 0 .. 1 0 0 .. 0 1 .. 1 0 0 .. 1 0 .. 1 0 0 .. 1 0 .. 1 0 1 .. 1 0 .. 1
39h
HD Adaptive Filter Gain 2
HD Adaptive Filter Gain 2 Value A
Gain A = 0 Gain A = +1 ...... Gain A = +7 Gain A = -8 ...... Gain A = -1 Gain B = 0 Gain B = +1 ....... Gain B = +7 Gain B = -8 ........ Gain B = -1
00h
HD Adaptive Filter Gain 2 Value B
0 0 .. 0 1 .. 1
0 0 .. 1 0 .. 1
0 0 .. 1 0 .. 1
0 1 .. 1 0 .. 1 0 0 .. 0 1 .. 1 0 0 .. 1 0 .. 1 0 0 .. 1 0 .. 1 0 1 .. 1 0 .. 1
3Ah
HD Adaptive Filter Gain 3
HD Adaptive Filter Gain 3 Value A
Gain A = 0 Gain A = +1 ...... Gain A = +7 Gain A = -8 ...... Gain A = -1 Gain B = 0 Gain B = +1 ....... Gain B = +7 Gain B = -8 ........
00h
HD Adaptive Filter Gain 3 Value B
0 0 .. 0 1 ..
0 0 .. 1 0 .. 1 x x x
0 0 .. 1 0 .. 1 x x x
0 1 .. 1 0 .. 1 x x x x x x x x x x x x x x x
3Bh 3Ch 3Dh
HD Adaptive Filter Threshold A HD Adaptive Filter Threshold B HD Adaptive Filter Threshold C
HD Adaptive Filter Threshold A Value HD Adaptive Filter Threshold B Value HD Adaptive Filter Threshold C Value
1 x x x
Gain B = -1 Threshold A Threshold B Threshold C
00h 00h 00h
REV. A
-23-
ADV7310/ADV7311
SR7- SR0 Register
3Eh 3Fh 40h SD Mode Register 0
Bit Description
Reserved Reserved SD Standard
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset Values
00h 00h
0 0 1 1
0 1 0 1
NTSC PAL B, D, G, H, I PAL M PAL N LPF NTSC LPF PAL Notch NTSC Notch PAL SSAF Luma Luma CIF Luma QCIF Reserved 1.3 MHz 0.65 MHz 1.0 MHz 2.0 MHz Reserved Chroma CIF Chroma QCIF 3.0 MHz
00h
SD Luma Filter
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
SD Chroma Filter
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
41h 42h
SD Mode Register 1
Reserved SD PrPb SSAF SD DAC Output 1 SD DAC Output 2 SD Pedestal SD Square Pixel SD VCR FF/RW Sync SD Pixel Data Valid SD SAV/EAV Step Edge Control 0 1 0 1
Disabled Enabled Refer to output configuration section Refer to output configuration section Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled
00h 08h
43h
SD Mode Register 2
SD Pedestal YPrPb Output SD Output Levels Y SD Output Levels PrPb 0 0 1 1 SD VBI Open SD CC Field Control 0 0 1 1 Reserved 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1
No pedestal on YUV 7.5 IRE pedestal on YUV Y = 700 mV/300 mV Y = 714 mV/286 mV 700 mV p-p[PAL]; 1000 mV p-p[NTSC] 700 mV p-p 1000 mV p-p 648 mV p-p Disabled Enabled CC disabled CC on odd field only CC on odd field only CC on both fields Reserved
00h
-24-
REV. A
ADV7310/ADV7311
SR7- SR0 Register
44h SD Mode Register 3
Bit Description
SD VSYNC-3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 1
Register Setting
Disabled VSYNC = 2.5 lines [PAL] VSYNC = 3 lines [NTSC] Genlock disabled Subcarrier Reset Timing Reset RTC enabled 720 pixels 710 [NTSC]/702[PAL] Chroma enabled Chroma disabled Enabled Disabled Disabled Enabled DAC A = Luma, DAC B = Chroma DAC A = Chroma, DAC B = Luma
Reset Values
00h
SD RTC/TR/SCR
0 0 1 1
0 1 0 1
SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 0 1 45h 46h 47h Reserved Reserved SD Mode Register 4 SD PrPb Scale SD Y Scale SD Hue Adjust SD Brightness SD Luma SSAF Gain Reserved Reserved Reserved 48h SD Mode Register 5 Reserved Reserved SD Double Buffering SD Input Format 0 0 1 1 SD Digital Noise Reduction SD Gamma Control SD Gamma Curve 49h SD Mode Register 6 SD Undershoot Limiter 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1
0 1
00h 00h 0 1 0 1 0 1 0 1 Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled 0 must be written to this bit 0 must be written to this bit 0 must be written to this bit 0 0 0 1 0 1 0 1 0 must be written to this bit Disabled Enabled 8-bit Input 16-bit Input 10-bit Input 20-bit Input Disabled Enabled Disabled Enabled Gamma Curve A Gamma Curve B 0 0 1 1 Reserved SD Black Burst Output on DAC Luma SD Chroma Delay 0 0 1 1 Reserved Reserved 0 0 0 1 0 1 0 0 1 0 1 0 1 Disabled - 11 IRE - 6 IRE - 1.5 IRE 0 must be written to this bit Disabled Enabled Disabled 4 clk cycles 8 clk cycles Reserved 0 must be written to this bit 0 must be written to this bit 00h 00h 00h
REV. A
-25-
ADV7310/ADV7311
SR7- SR0 Register
4Ah SD Timing Register 0
Bit Description
SD Slave/Master Mode SD Timing Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0 1
Register Setting
Slave Mode Master Mode Mode 0 Mode 1 Mode 2 Mode 3 Enabled Disabled No delay 2 clk cycles 4 clk cycles 6 clk cycles - 40 IRE - 7.5 IRE
Reset Values
08h
0 0 1 1
0 1 0 1
SD BLANK Input SD Luma Delay 0 0 1 1 SD Min. Luma Value SD Timing Reset 4Bh SD Timing Register 1 SD HSYNC Width x 0 1 0 0 0 0 1 0 1
0 1
0
0
0 0 0 1 1
0 0 1 0 1
A low-high-low transition will reset the internal SD timing counters Ta = 1 clk cycle Ta = 4 clk cycles Ta = 16 clk cycles Ta = 128 clk cycles Tb = 0 clk cycle Tb = 4 clk cycles Tb = 8 clk cycles Tb = 18 clk cycles Tc = Tb Tc = Tb + 32 us 1 clk cycle 4 clk cycles 16 clk cycles 128 clk cycles 0 clk cycles 1 clk cycle 2 clk cycles 00h
SD HSYNC to VSYNC delay
0 0 1 1
0 1 0 1
SD HSYNC to VSYNC Rising Edge Delay [Mode 1 Only] VSYNC Width [Mode 2 Only]
x x 0 0 1 1
0 1 0 1 0 1
HSYNC to Pixel Data Adjust
0 0 1
0 1 0 1 x x x x x x x x x 16 24 16 24 x x x x x x x x x 15 23 15 23 x x x x x x x x x 14 22 14 22 x x x x x x x x x 13 21 13 21 x x x x x x x x x 12 20 12 20 x x x x x x x x x 11 19 11 19 x x x x x x x x x 10 18 10 18
4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h
SD FSC Register 0 SD FSC Register 1 SD FSC Register 2 SD FSC Register 3 SD FSC Phase SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Closed Captioning SD Pedestal Register 0 SD Pedestal Register 1 SD Pedestal Register 2 SD Pedestal Register 3 Extended Data on Even Fields Extended Data on Even Fields Data on Odd Fields Data on Odd Fields Pedestal on Odd Fields Pedestal on Odd Fields Pedestal on Even Fields Pedestal on Even Fields
1 x x x x x x x x x 17 25 17 25
3 clk cycles Subcarrier Frequency Bit 7-0 Subcarrier Frequency Bit 15-8 Subcarrier Frequency Bit 23-16 Subcarrier Frequency Bit 31-24 Subcarrier Phase Bit 9-2 Extended Data Bit 7-0 Extended Data Bit 15-8 Data Bit 7-0 Data Bit 15-8 Setting any of these bits to 1 will disable pedestal on the line number indicated by the bit settings
16h 7Ch F0h 21h 00h 00h 00h 00h 00h 00h 00h 00h 00h
LINE 1 HSYNC
LINE 313
LINE 314
tA tB tC
VSYNC
Figure 21. Timing Register 1 in PAL Mode
-26-
REV. A
ADV7310/ADV7311
SR7- SR0 Register
59h SD CGMS/WSS 0
Bit Description
SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS
Bit 7
Bit 6
Bit 5
Bit 4
0 1
Bit 3
19
Bit 2
18
Bit 1
17
Bit 0
16
Register Setting
CGMS data bits C19-C16 Disabled Enabled Disabled Enabled Disabled Enabled Disabled
Reset Values
00h
0 1 0 1 0 1 13 15 14 6 5 4 3 x x x x x x x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 2 x 1 x 0 x 12 11 10 9 8
5Ah
SD CGMS/WSS 1
SD CGMS/WSS Data
Enabled CGMS data bits C13-C8 or WSS data bits C13-C8 CGMS data bits C15-C14 CGMS/WSS data bits C7-C0 SD Y Scale Bit 1-0 SD U Scale Bit 1-0 SD V Scale Bit 1-0 Subcarrier Phase Bits 1-0 SD Y Scale Bit 7-2 SD V Scale Bit 7-2 SD U Scale Bit 7-2 SD Hue Adjust Bit 7-0 SD Brightness Bit 6-0 Disabled Enabled -4 dB 0 dB +4 dB No gain +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1] No gain +1/16 [-1/8] +2/16 [-2/8] +3/16 [-3/8] +4/16 [-4/8] +5/16 [-5/8] +6/16 [-6/8] +7/16 [-7/8] +8/16 [-1]
00h 00h 00h
5Bh 5Ch
SD CGMS/WSS 2 SD LSB Register
SD CGMS/WSS Data SD LSB for Y Scale Value SD LSB for U Scale Value SD LSB for V Scale Value
7
5Dh 5Eh 5Fh 60h 61h
SD Y Scale Register SD V Scale Register SD U Scale Register SD Hue Register SD Brightness/WSS
SD LSB for FSC Phase SD Y Scale Value SD V Scale Value SD U Scale Value SD Hue Adjust Value SD Brightness Value SD Blank WSS Data SD Luma SSAF Gain/Attenuation Coring Gain Border
00h 00h 00h 00h 00h Line 23 00h
62h
SD Luma SSAF
63h
SD DNR 0
00h In DNR mode, the values in brackets apply.
Coring Gain Data
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0 0 0 ... 1 1
0 1 0 1 0 1 0 1 0 0 0 ... 1 1 0 0 ... 1 1 0 0 ... 1 1 0 0 ... 1 1 0 1 ... 0 1
64h
SD DNR 1
DNR Threshold
0 1 ... 62 63 2 pixels 4 pixels 8 pixels 16 pixels
00h
Border Area Block Size Control 0 1
0 1
REV. A
-27-
ADV7310/ADV7311
SR7- SR0 Register
65h SD DNR 2
Bit Description
DNR Input Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
0 0 0 1
Bit 1
0 1 1 0
Bit 0
1 0 1 0
Register Setting
Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset 1 pixel offset ... 14 pixel offset
Reset Values
00h
DNR Mode DNR Block Offset 0 0 ... 1 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma A SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Gamma B SD Brightness Detect Field Count Register SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve A Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Gamma Curve B Data Points SD Brightness Value Field Count Reserved Reserved Reserved Revision Code 7Ch 10-Bit Input x 0 x 0 1 x x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 1 x x x x x x x x x x x x x x x x x x x x x 0 0 ... 1 1 x x x x x x x x x x x x x x x x x x x x x
0 1 0 1 ... 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 1 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
15 pixel offset A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Read only Read only 0 must be written to this bit 0 must be written to this bit 0 must be written to this bit Read only Must write this for 10-bit data input (SD, PS, HD)
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
00h
-28-
REV. A
ADV7310/ADV7311
SR7SR0
7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h
Register
Reserved Reserved Reserved Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision Macrovision
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset Values
MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bits MV Control Bit
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x 0
x x x x x x x x x x x x x x x x x x 0 must be written to these bits
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
NOTE Macrovision registers only on the ADV7310.
REV. A
-29-
ADV7310/ADV7311
INPUT CONFIGURATION
When 10-bit input data is applied, the following bits must be set to 1: Address 0x7C, Bit 1 (Global 10-Bit Enable) Address 0x13, Bit 2 (HD 10-Bit Enable) Address 0x48, Bit 4 (SD 10-Bit Enable) Note that the ADV7310 defaults to simultaneous standard definition and progressive scan on power-up. Address[01h] : Input Mode = 011
Standard Definition Only Address[01h] : Input Mode = 000
MPEG2 DECODER YCrCb 27MHz Cb 10 Cr 10 INTERLACED TO PROGRESSIVE Y 10 3
ADV7310/ ADV7311
CLKIN_A C[9:0] S[9:0] Y[9:0] P_VSYNC P_HSYNC P_BLANK
Figure 23. Progressive Scan Input Mode
Simultaneous Standard Definition and Progressive Scan or HDTV Address[01h] : Input Mode 011(SD 10-Bit, PS 20-Bit) or 101(SD and HD, SD Oversampled), 110(SD and HD, HD Oversampled), Respectively
The 8-/10-bit multiplexed input data is input on Pins S9-S0 (or Y9-Y0, depending on Register Address 01h, Bit 7), with S0 being the LSB in 10-bit input mode. Input standards supported are ITU-R BT.601/656. In 16-bit input mode, the Y pixel data is input on Pins S9-S2 and CrCb data on Pins C9-C2. The 27 MHz clock input must be input on Pin CLKIN_A. Input sync signals are optional and are input on the S_VSYNC, S_HSYNC, and S_BLANK pins.
ADV7310/ ADV7311
3 MPEG2 DECODER 27MHz S_VSYNC S_HSYNC S_BLANK CLKIN_A
YCrCb, PS, HDTV, or any other HD data must be input in 4:2:2 format. In 4:2:2 input mode the HD Y data is input on Pins Y9-Y0 and the HD CrCb data on C9-C0. If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9-Y0 are used for the input port. The input data is to be input at 27 MHz, with the data being clocked on the rising and falling edge of the input clock. The input mode register at Address 01h is set accordingly. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE 296M[720p], or BTA-T1004, the async timing mode must be used. The 8- or 10-bit standard definition data must be compliant with ITU-R BT.601/656 in 4:2:2 format. Standard definition data is input on Pins S9-S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9-S2. The clock input for SD must be input on CLKIN_A and the clock input for HD must be input on CLKIN_B. Synchronization signals are optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and S_BLANK. HD syncs on Pins P_VSYNC, P_HSYNC, and P_BLANK.
ADV7310/ ADV7311
MPEG2 DECODER 3 27MHz YCrCb 10 S_VSYNC S_HSYNC S_BLANK CLKIN_A S[9:0]
YCrCb
10
S[9:0] OR Y[9:0]*
*SELECTED BY ADDRESS 0x01 BIT 7
Figure 22. SD Only Input Mode
Progressive Scan Only or HDTV Only Address[01h] Input Mode 001 or 010, Respectively
YCrCb progressive scan, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is input on Pins Y9-Y0 and the CrCb data on Pins C9-C0. In 4:4:4 input mode, Y data is input on Pins Y9-Y0, Cb data on Pins C9-C0, and Cr data on Pins S9-S0. If the YCrCb data does not conform to SMPTE 293M (525p), ITU-R BT.1358M (625p), SMPTE 274M[1080i], SMPTE 296M[720p], or BTA-T1004/1362, the async timing mode must be used. RGB data can only be input in 4:4:4 format in PS input mode only or HDTV input mode only when HD RGB input is enabled. G data is input on Pins Y9-Y0, R data on S9-S0, and B data on C9-C0. The clock signal must be input on Pin CLKIN_A.
CrCb 10 INTERLACED TO Y 10 PROGRESSIVE 3 27MHz
C[9:0] Y[9:0] P_VSYNC P_HSYNC P_BLANK CLKIN_B
Figure 24. Simultaneous PS and SD Input
-30-
REV. A
ADV7310/ADV7311
ADV7310/ ADV7311
3 SDTV DECODER 27MHz YCrCb 10 HDTV DECODER 1080i OR 720p S_VSYNC S_HSYNC S_BLANK CLKIN_A S[9:0]
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE. CLKIN_B
Y9-Y0
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
CrCb 10 Y 10 3 74.25MHz
C[9:0] Y[9:0] P_VSYNC P_HSYNC P_BLANK CLKIN_B
Figure 27a. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
CLKIN_B
Y9-Y0
3FF
00
00
XY
Y0
Cb0
Y1
Cr0
Figure 25. Simultaneous HD and SD Input
If in simultaneous SD/HD input mode the two clock phases differ by less than 9.25 ns or more than 27.75 ns, the CLOCK ALIGN bit [Address 01h Bit 3] must be set accordingly. If the application uses the same clock source for both SD and PS, the CLOCK ALIGN bit must be set since the phase difference between both inputs is less than 9.25 ns.
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 27b. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
CLKIN
PIXEL INPUT DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
CLKIN_A
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
CLKIN_B
tDELAY tDELAY
9.25ns OR 27.75ns
Figure 27c. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2 DECODER YCrCb 27MHz OR 54MHz
Figure 26. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz Address[01h] : Input Mode 100 or 111, Respectively
ADV7310/ ADV7311
CLKIN_A
YCrCb progressive scan data can be input at 27 MHz or 54 MHz. The input data is interleaved onto a single 8-/10-bit bus and is input on Pins Y9-Y0. When a 27 MHz clock is supplied, the data is clocked in on the rising and falling edge of the input clock and CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly. The following figures show the possible conditions: (a) Cb data on the rising edge and (b) Y data on the rising edge.
INTERLACED TO PROGRESSIVE
YCrCb
10 3
Y[9:0] P_VSYNC P_HSYNC P_BLANK
Figure 28. 1
10-Bit PS at 27 MHz or 54 MHz
Table I provides an overview of all possible input configurations.
REV. A
-31-
ADV7310/ADV7311
Table I. Input Configurations
Input Format
ITU-R BT.656
Total Bits
8 10 16 20 8 10 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:4:4
Input Video
YCrCb YCrCb Y CrCb Y CrCb YCrCb YCrCb YCrCb YCrCb YCrCb YCrCb Y CrCb Y CrCb Y Cb Cr Y Cb Cr
Input Pins
S9-S2 [MSB = S9] S9-S0 [MSB = S9] S9-S2 [MSB = S9] Y9-Y2 [MSB = Y9] S9-S0 [MSB = S9] Y9-Y0 [MSB = Y9] Y9-Y2 [MSB = Y9] Y9-Y0 [MSB = Y9] Y9-Y2 [MSB = Y9] Y9-Y0 [MSB = Y9] Y9-Y2 [MSB = Y9] Y9-Y0 [MSB = Y9] Y9-Y2 [MSB = Y9] C9-C2 [MSB = C9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9] Y9-Y2 [MSB = Y9] C9-C2 [MSB = C9] S9-S2 [MSB = S9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9] S9-S0 [MSB = S9] Y9-Y2 [MSB = Y9] C9-Y2 [MSB = C9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9] Y9-Y2 [MSB = Y9] C9-Y2 [MSB = C9] S9-S2 [MSB = S9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9] S9-S0 [MSB = S9] Y9-Y2 [MSB = Y9] C9-C2 [MSB = C9] S9-S2 [MSB = S9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9] S9-S0 [MSB = S9] S9-S2 [MSB = S9] Y9-Y2 [MSB = Y9] S9-S0 [MSB = S9] Y9-Y0 [MSB = Y9] S9-S2 [MSB = S9] Y9-Y2 [MSB = Y9] C9-C2 [MSB = C9] S9-S0 [MSB = S9] Y9-Y0 [MSB = Y9] C9-C0 [MSB = C9]
Subaddress
01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 48h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 01h 13h 15h 01h 13h 15h 01h 13h 48h 01h 13h 48h 01h 13h 48h 01h 13h 48h
Register Setting
00h 00h 00h 10h 00h 08h 00h 18h 80h 00h 80h 10h 10h 40h 10h 44h 70h 40h 70h 44h 10h 40h 10h 44h 10h 00h 10h 04h 20h 40h 20h 44h 20h 00h 20h 04h 10h or 20h 00h 02h 10h or 20h 04h 02h 40h 40h 00h 40h 44h 10h 30h or 50h or 60h 40h 00h 30h or 50h or 60h 44h 10h
PS Only
8 [27 MHz clock] 10 [27 MHz clock] 8 [54 MHz clock] 10 [54 MHz clock] 16 20 24
30
4:4:4
HDTV Only
16
4:2:2
Y CrCb Y CrCb Y Cb Cr
20 24
4:2:2 4:4:4
30
4:4:4
Y Cb Cr G B R G B R
HD RGB
24
4:4:4
30
4:4:4
ITU-R BT.656 and PS ITU-R BT.656 and PS
8 8 10 10
4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2 4:2:2
YCrCb YCrCb YCrCb YCrCb YCrCb Y CrCb YCrCb Y CrCb
ITU-R BT.656 and PS or HDTV
8 16
ITU-R BT.656 and PS or HDTV
10 20
-32-
REV. A
ADV7310/ADV7311
OUTPUT CONFIGURATION
The tables below demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.
Table II. Output Configuration in SD Only Mode
RGB/YUV Output 02h, Bit 5
0 0 0 0 1 1 1 1
SD DAC Output 1 42h, Bit 2
0 0 1 1 0 0 1 1
SD DAC Output 2 42h, Bit 1
0 1 0 1 0 1 0 1
DAC A
CVBS G G CVBS CVBS Y Y CVBS
DAC B
Luma B Luma B Luma U Luma U
DAC C
Chroma R Chroma R Chroma V Chroma V
DAC D
G CVBS CVBS G Y CVBS CVBS Y
DAC E
B Luma B Luma U Luma U Luma
DAC F
R Chroma R Chroma V Chroma V Chroma
Luma/Chroma Swap 44h, Bit 7
0 1 Table as above Table above with all Luma/Chroma instances swapped
Table III. Output Configuration in HD/PS Only Mode
HD/PS Input Format
YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:2:2 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4 RGB 4:4:4
HD/PS RGB Input 15h, Bit 1
0 0 0 0 0 0 0 0 1 1 1 1
RGB/YPrPb Output 02h, Bit 5
0 0 1 1 0 0 1 1 0 0 1 1
HD/PS Color Swap 15h, Bit 3
0 1 0 1 0 1 0 1 0 1 0 1
DAC A
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DAC B
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DAC C
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
DAC D
G G Y Y G G Y Y G G G G
DAC E
B R Pb Pr B R Pb Pr B R B R
DAC F
R B Pr Pb R B Pr Pb R B R B
Table IV. Output Configuration in Simultaneous SD and HD/PS Only Mode
Input Formats
ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2 ITU-R.BT656 and HD YCrCb in 4:2:2
RGB/YPrPb Output 02h, Bit 5
0 0 1 1
HD/PS Color Swap 15h, Bit 3
0 1 0 1
DAC A
CVBS CVBS CVBS CVBS
DAC B
Luma Luma Luma Luma
DAC C
Chroma Chroma Chroma Chroma
DAC D
G G Y Y
DAC E
B R Pb Pr
DAC F
R B Pr Pb
REV. A
-33-
ADV7310/ADV7311
TIMING MODES HD Async Timing Mode [Subaddress 10h, Bit 3, 2]
In async mode, the PLL must be turned off [Subaddress 00h, Bit 1 = 1]. Figures 29a and 29b show examples of how to program the ADV7310/ADV7311 to accept a different high definition standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358. The following truth table must be followed when programming the control signals in async timing mode. For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
For any input data that does not conform to the standards selectable in input mode, Subaddress 10h, asynchronous timing mode can be used to interface to the ADV7310/ADV7311. Timing control signals for HSYNC, VSYNC, and BLANK have to be programmed by the user. Macrovision and programmable oversampling rates are not available in async timing mode.
CLK P_HSYNC PROGRAMMABLE INPUT TIMING
P_VSYNC
P_BLANK SET ADDRESS 10h, BIT 6 TO 1
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG OUTPUT
81 a
66 b
66 c
243 d
1920 e
Figure 29a. Async Timing Mode--Programming Input Control Signals for SMPTE 295M Compatibility
CLK P_HSYNC 0 1 P_BLANK SET ADDRESS 10h, BIT 6 TO 1
P_VSYNC
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG OUTPUT
a
b
c
d
e
Figure 29b. Async Timing Mode--Programming Input Control Signals for Bilevel Sync Signal
-34-
REV. A
ADV7310/ADV7311
Table V. Async Timing Mode Truth Table
P_HSYNC 10 0 01 1 1
P_VSYNC 0 01 0 or 1 0 or 1 0 or 1
P_BLANK* 0 or 1 0 or 1 0 01 10
Reference 50% point of falling edge of trilevel horizontal sync signal 25% point of rising edge of trilevel horizontal sync signal 50% point of falling edge of trilevel horizontal sync signal 50% start of active video 50% end of active video
Reference in Figure 29 a b c d e
*When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
HD TIMING RESET
A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 14h, Bit 0] from 0 to 1. In this state the horizontal and vertical counters will remain reset. When this bit is set back to 0, the internal counters will commence counting again.
The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the HD timing counters only.
REV. A
-35-
ADV7310/ADV7311
SD Real-Time Control, Subcarrier Reset, and Timing Reset [Subaddress 44h, Bit 2, 1]
This reset signal will have to be held high for a minimum of one clock cycle. Since the field counter is not reset, it is recommended that the reset signal be applied in Field 7 [PAL] or Field 3 [NTSC]. The reset of the phase will then occur on the next field, i.e., Field 1, being lined up correctly with the internal counters. The field count register at Address 7Bh can be used to identify the number of the active field. c. In RTC mode, the ADV7310/ADV7311 can be used to lock to an external video source. The real-time control mode allows the ADV7310/ADV7311 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital data stream in the RTC format, such as an ADV7183A video decoder (see Figure 32), the part will automatically change to the compensated subcarrier frequency on a line by line basis. This digital data stream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00h should be written into all four subcarrier frequency registers when this mode is used.
Together with the RTC_SCR_TR pin and SD Mode Register 3 [Address 44h, Bit 1, 2], the ADV7310/ADV7311 can be used in (a) timing reset mode, (b) subcarrier phase reset mode, or (c) RTC mode. a. A timing reset is achieved in a low-to-high transition on the RTC_SCR_TR pin (Pin 31). In this state, the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will commence counting again, the field count will start on Field 1, and the subcarrier phase will be reset. The minimum time the pin has to be held high is one clock cycle; otherwise, this reset signal might not be recognized. This timing reset applies to the SD timing counters only. b. In subcarrier phase reset, a low-to-high transition on the RTC_SCR_TR pin (Pin 31) will reset the subcarrier phase to zero on the field following the subcarrier phase reset when the SD RTC/TR/SCR control bits at Address 44h are set to 01.
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 4 OR 8
307
310
313
320
NO TIMING RESET APPLIED DISPLAY START OF FIELD 1 FSC PHASE = FIELD 1
307
1
2
3
4
5
6
7
21
TIMING RESET PULSE TIMING RESET APPLIED
Figure 30. Timing Reset Timing Diagram
DISPLAY START OF FIELD 4 OR 8 FSC PHASE = FIELD 4 OR 8
307 NO FSC RESET APPLIED
310
313
320
DISPLAY
START OF FIELD 4 OR 8
FSC PHASE = FIELD 1
307
310
313
320
FSC RESET PULSE FSC RESET APPLIED
Figure 31. Subcarrier Reset Timing Diagram
-36-
REV. A
ADV7310/ADV7311
Reset Sequence
A reset is activated with a high-to-low transition on the RESET pin [Pin 33] according to the timing specifications. The ADV7310/ ADV7311 will revert to the default output configuration. Figure 32 illustrates the RESET sequence timing.
SD VCR FF/RW Sync [Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, i.e., in fast forward or rewind modes.
In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync signal usually occurs after the total number of lines/fields are reached. Conventionally this means that the output video will have corrupted field signals, one generated by the incoming video and one generated when the internal lines/field counters reach the end of a field. When the VCR FF/RW sync control is enabled [Subaddress 42h Bit 5] the lines/field counters are updated according to the incoming VSYNC signal and the analog output matches the incoming VSYNC signal. This control is available in all slave timing modes except Slave Mode 0.
ADV7310/ ADV7311
CLKIN_A LCC1 COMPOSITE VIDEO1 DAC A DAC B GLL RTC_SCR_TR DAC C DAC D Y9-Y0/S9-S05 DAC E DAC F 14 BITS H/L TRANSITION SUBCARRIER COUNT START PHASE LOW 128 13 0 RTC TIME SLOT 01 14 19 VALID INVALID SAMPLE SAMPLE 8/LINE LOCKED CLOCK 6768 5 BITS RESERVED 4 BITS RESERVED SEQUENCE BIT3 21 FSC PLL INCREMENT2 0 RESET BIT4 RESERVED
ADV7183A
P19-P10 VIDEO DECODER
NOTES 1i.e., VCR OR CABLE 2F SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7310/ADV7311 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7310/ADV7311. 3SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 4RESET ADV7310/ADV7311 DDS 5SELECTED BY REGISTER ADDRESS 0x01 BIT 7
Figure 32. RTC Timing and Connections
RESET DACs A, B, C
XXXXXX
OFF
VALID VIDEO
DIGITAL TIMING
XXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
TIMING ACTIVE
PIXEL DATA VALID
Figure 33. RESET Timing Sequence
REV. A
-37-
ADV7310/ADV7311
Vertical Blanking Interval
The ADV7310/ADV7311 accept input data that contains VBI data [CGMS, WSS, VITS, and so on] in SD and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the ITU-R BT.1358 [625p] standard. For SD NTSC this data can be present on Lines 10 to 20, and in PAL on Lines 7 to 22. If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h, Bit 4 for SD], VBI data is not present at the output and the entire VBI is blanked. These control bits are valid in all master and slave modes. In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten, and it is possible to use VBI in this timing mode as well. In Slave Mode 1 or 2, the BLANK control bit must be set to enabled [Address 4Ah, Bit 3] to allow VBI data to pass through the ADV7310/ADV7311. Otherwise, the ADV7310/ADV7311 automatically blanks the VBI to standard. If CGMS is enabled and VBI is disabled, the CGMS data will nevertheless be available at the output.
Subcarrier Frequency Registers [Subaddress 4Ch-4Fh]
Four 8-bit registers are used to set up the subcarrier frequency. The value of these registers is calculated using the equation Subcarrier Frequency Register = Number of subcarrier frequency values in one video line Number of 27 MHz clk cycles in one video line
*Rounded to the nearest integer
223 *
For example, in NTSC mode, 227.5 23 Subcarrier FrequencyValue = x 2 = 569408542 1716 Subcarrier Register Value = 21F07C1Eh SD FSC Register 0: 1Eh SD FSC Register 1: 7Ch SD FSC Register 2: F0h SD FSC Register 3: 21h Refer to the MPU Port Description section for more details on how to access the subcarrier frequency registers.
Square Pixel Timing [Register 42h, Bit 4]
In square pixel mode, the following timing diagrams apply.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F0 0X818 1 Y Y r F0 0Y000 0 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 272 CLOCK 4 CLOCK 344 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b 0000F00Yb r
NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz)
4 CLOCK
4 CLOCK 1280 CLOCK 4 CLOCK 1536 CLOCK START OF ACTIVE VIDEO LINE
Figure 34. EAV/SAV Embedded Timing
HSYNC
FIELD
PAL = 44 CLOCK CYCLES NTSC = 44 CLOCK CYCLES
BLANK
PIXEL DATA
Cb
Y
Cr
Y
PAL = 136 CLOCK CYCLES NTSC = 208 CLOCK CYCLES
Figure 35. Active Pixel Timing
-38-
REV. A
ADV7310/ADV7311
FILTER SECTION HD Sinc Filter
0.5 0.4
Table VI shows an overview of the programmable filters available on the ADV7310/ADV7311.
Table VI. Selectable Filters
0.3 0.2
GAIN (dB)
Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.0 MHz SD Chroma 3.0 MHz SD Chroma CIF SD Chroma QCIF SD UV SSAF HD Chroma Input HD Sinc Filter HD Chroma SSAF
Subaddress 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h 40h 42h 13h 13h 13h
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30
Figure 36. HD Sinc Filter Enabled
0.5 0.4 0.3 0.2
GAIN (dB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 5 10 15 20 FREQUENCY (MHz) 25 30
Figure 37. HD Sinc Filter Disabled
REV. A
-39-
ADV7310/ADV7311
SD Internal Filter Response [Subaddress 40h; Subaddress 42, Bit 0] Table VII. Internal Filter Specifications
The Y filter supports several different frequency responses including two low-pass responses, two notch responses, an extended (SSAF) response with or without gain boost attenuation, a CIF response, and a QCIF response. The UV filter supports several different frequency responses including six low-pass responses, a CIF response, and a QCIF response, as can be seen in the figures on the following pages. If SD SSAF gain is enabled, there is the option of 12 responses in the range from -4 dB to +4 dB [Subaddress 47, Bit 4]. The desired response can be chosen by the user by programming the correct value via the I2C [Subaddress 62h]. The variation of frequency responses can be seen in the figures on the following pages. In addition to the chroma filters listed in Table VII, the ADV7310/ADV7311 contains an SSAF filter specifically designed for and applicable to the color difference component outputs, U and V. This filter has a cutoff frequency of about 2.7 MHz and -40 dB at 3.8 MHz, as can be seen in Figure 38. This filter can be controlled with Address 42h, Bit 0. If this filter is disabled, the selectable chroma filters shown in Table VII can be used for the CVBS or Luma/Chroma signal.
Filter Luma LPF NTSC Luma LPF PAL Luma Notch NTSC Luma Notch PAL Luma SSAF Luma CIF Luma QCIF Chroma 0.65 MHz Chroma 1.0 MHz Chroma 1.3 MHz Chroma 2.0 MHz Chroma 3.0 MHz Chroma CIF Chroma QCIF
Pass-Band Ripple1 (dB) 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic Monotonic Monotonic 0.09 0.048 Monotonic Monotonic Monotonic
3 dB Bandwidth2 (MHz) 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5 0.65 1 1.395 2.2 3.2 0.65 0.5
NOTES 1 Pass-band ripple is the maximum fluctuation from the 0 dB response in the pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz) frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to infinity for a notch filter, where fc, f1, and f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency.
EXTENDED UV FILTER MODE 0
-10
GAIN (dB)
-20
-30
-40
-50
-60 0 1 2 3 4 5 6 FREQUENCY (MHz)
Figure 38. UV SSAF Filter
-40-
REV. A
Typical Performance Characteristics-ADV7310/ADV7311
PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4
1.0 0.5
Y PASS BAND IN PS OVERSAMPLING MODE
0 -10 0 -20 -0.5
GAIN (dB)
GAIN (dB)
-30 -40 -50 -60 -70 -80
-1.0 -1.5 -2.0 -2.5 -3.0
0
20
40
60
80 100 120 140 FREQUENCY (MHz)
160
180
200
0
2
4
6 8 FREQUENCY (MHz)
10
12
TPC 1. PS--UV 8x Oversampling Filter (Linear)
TPC 4. PS--Y 8x Oversampling Filter (Pass Band)
PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4
Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE
0 -10 -20
0 -10 -20
GAIN (dB)
-40 -50 -60 -70 -80
GAIN (dB)
0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200
-30
-30 -40 -50 -60 -70 -80
0
20
40
60 80 100 FREQUENCY (MHz)
120
140
TPC 2. PS--UV 8x Oversampling Filter (SSAF)
Y RESPONSE IN PS OVERSAMPLING MODE
TPC 5. HDTV--UV (2x Oversampling Filter)
Y RESPONSE IN HDTV OVERSAMPLING MODE
0 -10 -20
0 -10 -20
GAIN (dB)
-40 -50 -60 -70 -80
GAIN (dB)
0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200
-30
-30 -40 -50 -60 -70 -80
0
20
40
60 80 100 FREQUENCY (MHz)
120
140
TPC 3. PS--Y (8x Oversampling Filter)
TPC 6. HDTV--Y (2x Oversampling Filter)
REV. A
-41-
ADV7310/ADV7311
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12
MAGNITUDE (dB)
TPC 7. Luma NTSC Low-Pass Filter
0 0 -10 -10
MAGNITUDE (dB)
MAGNITUDE (dB)
TPC 10. Luma PAL Notch Filter
Y RESPONSE IN SD OVERSAMPLING MODE
-20
-20
GAIN (dB)
0 2 4 6 8 FREQUENCY (MHz) 10 12
-30 -40 -50 -60
-30 -40 -50 -60 -70
-70 -80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200
TPC 8. Luma PAL Low-Pass Filter
0 0 -10 -10
MAGNITUDE (dB)
TPC 11. Y--16x Oversampling Filter
-20 -30 -40 -50 -60 -60 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12 -70 0 2 4 6 8 FREQUENCY (MHz) 10 12
MAGNITUDE (dB)
-20 -30 -40 -50
TPC 9. Luma NTSC Notch Filter
TPC 12. Luma SSAF Filter up to 12 MHz
-42-
REV. A
ADV7310/ADV7311
4 2 0 0 -10 -20 -30 -40 -50 -60 -70 0 1 2 3 4 5 6 7 0 2 4 6 FREQUENCY (MHz) 8 10 12 FREQUENCY (MHz)
MAGNITUDE (dB)
-2 -4 -6 -8 -10 -12
TPC 13. Luma SSAF Filter--Programmable Responses
5 0 -10 -20 -30 -40 -50 0 -60 -70 0 1 2 3 4 5 6 7 0
MAGNITUDE (dB)
TPC 16. Luma CIF Low-Pass Filter
4
MAGNITUDE (dB)
3
2
1
-1 FREQUENCY (MHz)
MAGNITUDE (dB)
2
4
6 FREQUENCY (MHz)
8
10
12
TPC 14. Luma SSAF Filter--Programmable Gain
1
TPC 17. Luma QCIF Low-Pass Filter
0
0
-10
MAGNITUDE (dB)
-1
MAGNITUDE (dB)
0 1 2 3 4 5 6 7
-20 -30 -40 -50
-2
-3
-4
-60
-5 FREQUENCY (MHz)
-70 0 2 4 6 FREQUENCY (MHz) 8 10 12
TPC 15. Luma SSAF Filter--Programmable Attenuation
TPC 18. Chroma 3.0 MHz Low-Pass Filter
REV. A
-43-
ADV7310/ADV7311
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 FREQUENCY (MHz) 8 10 12 0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 FREQUENCY (MHz) 8 10 12
MAGNITUDE (dB)
TPC 19. Chroma 2.0 MHz Low-Pass Filter
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 FREQUENCY (MHz) 8 10 12
MAGNITUDE (dB) MAGNITUDE (dB)
TPC 22. Chroma 0.65 MHz Low-Pass Filter
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 FREQUENCY (MHz) 8 10 12
MAGNITUDE (dB)
TPC 20. Chroma 1.3 MHz Low-Pass Filter
0 -10 -20 -30 -40 -50 -60 -70 0 2 4 6 FREQUENCY (MHz) 8 10 12 0 -10 -20 -30 -40 -50 -60 -70 0
TPC 23. Chroma CIF Low-Pass Filter
MAGNITUDE (dB)
MAGNITUDE (dB)
2
4
6 FREQUENCY (MHz)
8
10
12
TPC 21. Chroma 1.0 MHz Low-Pass Filter
TPC 24. Chroma QCIF Low-Pass Filter
-44-
REV. A
ADV7310/ADV7311
COLOR CONTROLS AND RGB MATRIX HD Y Level, HD Cr Level, HD Cb Level [Subaddress 16h-18h] Programming the RGB Matrix
Three 8-bit registers at Address 16h, 17h, 18h are used to program the output color of the internal HD test pattern generator, be it the lines of the cross hatch pattern or the uniform field test pattern. They are not functional as color controls on external pixel data input. For this purpose the RGB matrix is used. The standard used for the values for Y and the color difference signals to obtain white, black, and the saturated primary and complementary colors conforms to the ITU-R BT.601-4 standard. Table VIII shows sample color values to be programmed into the color registers when Output Standard Selection is set to EIA 770.2.
Table VIII. Sample Color Values for EIA 770.2 Output Standard Selection
The RGB matrix should be enabled [Address 02h, Bit 3], the output should be set to RGB [Address 02h, Bit 5], sync on PrPb should be disabled [Address 15h, Bit 2], and sync on RGB is optional [Address 02h, Bit 4]. GY at address 03h and 05h control the output levels on the green signal, BU at 04h and 08h the blue signal output levels and RV at 04h and 09h the red output levels. To control YPrPb output levels, YUV output should be enabled [Address 02h, Bit 5]. In this case GY [Address 05h; Address 03, Bit 0-1] is used for the Y output, RV [Address 09; Address 04, Bit 0-1] is used for the Pr output, and BU [Address 08h; Address 04h, Bit 2-3] is used for the Pb output. If RGB output is selected the RGB matrix scaler uses the following equations:
G = GY x Y + GU x Pb + GV x Pr B = GY x Y + BU x Pb R = GY x Y + RV x Pr
Sample Color White Black Red Green Blue Yellow Cyan Magenta
Y Value 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A)
Cr Value 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE)
Cb Value 128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA)
If YPrPb output is selected the following equations are used:
Y = GY x Y U = BU x Pb V = RV x Pr
On power-up, the RGB matrix is programmed with the default values below.
Table IX. RGB Matrix Default Values
HD RGB Matrix [Subaddress 03h-09h]
Address 03h 04h 05h 06h 07h 08h 09h
Default 03h F0h 4Eh 0Eh 24h 92h 7Ch
When the programmable RGB matrix is disabled [Address 02h, Bit 3], the internal RGB matrix takes care of all YCrCb to YUV or RGB scaling according to the input standard programmed into the device. When the programmable RGB matrix is enabled, the color components are converted according to the 1080i standard [SMPTE 274M]:
Y' = 0.2126 R' + 0.7152G' + 0.0722 B' CB' = [0.5 / (1 - 0.0722)](B' - Y' ) CR' = [0.5 / (1 - 0.2126 )](R' - Y' )
This is reflected in the preprogrammed values for GY = 138Bh, GU = 93h, GV = 3B, BU = 248h, and RV = 1F0. If another input standard is used, the scale values for GY, GU, GV, BU, and RV have to be adjusted according to this input standard. The user must consider the fact that the color component conversion might use different scale values. For example, SMPTE 293M uses the following conversion:
Y' = 0.299 R' + 0.587 G' + 0.114 B' CB' = [0.5 / (1 - 0.114 )](B' - Y' ) CR' = [0.5 / (1 - 0.299)](R' - Y' )
When the programmable RGB matrix is not enabled, the ADV7310/ADV7311 automatically scales YCrCb inputs to all standards supported by this part.
SD Luma and Color Control [Subaddress 5Ch, 5Dh, 5Eh, 5Fh]
SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit wide control registers to scale the Y, U, and V output levels. Each of these registers represents the value required to scale the U or V level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of its initial level. The value of these 10 bits is calculated using the following equation: Y, U, or V ScalarValue = Scale Factor x 512 For example: Scale Factor = 1.18 Y, U, or V Scale Value = 1.18 x 512 = 665.6 Y, U, or V Scale Value = 665 (rounded to the nearest integer) Y, U, or V Scale Value = 1010 0110 01 b
The programmable RGB matrix can be used to control the HD output levels in cases where the video output does not conform to standard due to altering the DAC output stages such as termination resistors. The programmable RGB matrix is used for external HD data and is not functional when the HD test pattern is enabled.
REV. A
Address 5Ch, SD LSB Register = 15h Address 5Dh, SD Y Scale Register = A6h Address 5Eh, SD V Scale Register = A6h Address 5Fh, SD U Scale Register = A6h -45-
ADV7310/ADV7311
SD Hue Adjust Value [Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7310/ADV7311 provides a range of 22.5o increments of 0.17578125o. For normal operation (zero adjustment), this register is set to 80h. FFh and 00h represent the upper and lower limits (respectively) of adjustment attainable. (Hue Adjust) [o] = 0.17578125o x (HCR d - 128), for positive hue adjust value. For example, to adjust the hue by +4 , write 97h to the Hue Adjust Value register: 4 + 128 = 105d* = 97h 0.17578125
*rounded to the nearest integer
o
Standard: PAL. To add -7IRE brightness level, write 72h to Address 61h, SD brightness.
[ IREValue x 2.015631] =
[7 x 2.015631] = [14.109417] = 0001110b [0001110] into twos complement = [1110010] b = 72h
Table X. Brightness Control Values*
Setup Level In NTSC with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE
Setup Level In NTSC No Pedestal 15 IRE 7.5 IRE 0 IRE -7.5 IRE
Setup Level In PAL 15 IRE 7.5 IRE 0 IRE -7.5 IRE
SD Brightness 1Eh 0Fh 00h 71h
To adjust the hue by -4o, write 69h to the Hue Adjust Value register: -4 + 128 = 105d* = 69h 0.17578125
*rounded to the nearest integer
*Values in the range from 3Fh to 44h might result in an invalid output signal.
SD Brightness Detect [Subaddress 7Ah]
The ADV7310/ADV7311 allow monitoring of the brightness level of the incoming video data. Brightness detect is a read-only register.
Double Buffering [Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
SD Brightness Control [Subaddress 61h]
The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the scaled Y data. For NTSC with pedestal, the setup can vary from 0IRE to 22.5IRE. For NTSC without pedestal and PAL, the setup can vary from -7.5IRE to +15IRE. The brightness control register is an 8-bit register. Seven bits of this 8-bit register are used to control the brightness level. This brightness level can be a positive or negative value. For example: Standard: NTSC with Pedestal. To add +20IRE brightness level, write 28h to Address 61h, SD brightness.
Double buffered registers are updated once per field on the falling edge of the VSYNC signal. Double buffering improves the overall performance since modifications to register settings will not be made during active video, but take effect on the start of the active video. Double buffering can be activated on the following HD registers: HD Gamma A and Gamma B curves and HD CGMS registers. Double buffering can be activated on the following SD registers: SD Gamma A and Gamma B curves, SD Y Scale, SD U Scale, SD V Scale, SD Brightness, SD Closed Captioning, and SD Macrovision Bits 5-0.
[SD BrightnessValue ] h = [ IREValue x 2.015631] h = [20 x 2.015631] h = [40.31262] h = 28h
NTSC WITHOUT PEDESTAL 100 IRE +7.5 IRE
0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED NEGATIVE SETUP VALUE ADDED
-7.5 IRE
Figure 39. Examples of Brightness Control Values
-46-
REV. A
ADV7310/ADV7311
PROGRAMMABLE DAC GAIN CONTROL
DACs A, B, and C are controlled by REG 0A. DACs D, E, and F are controlled by REG 0B. The I2C control registers will adjust the output signal gain up or down from its absolute level.
CASE A
GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0Ah, 0Bh 700mV
In case A, the video output signal is gained. The absolute level of the sync tip and blanking level both increase with respect to the reference video output signal. The overall gain of the signal is increased from the reference signal. In case B, the video output signal is reduced. The absolute level of the sync tip and blanking level both decrease with respect to the reference video output signal. The overall gain of the signal is reduced from the reference signal. The range of this feature is specified for 7.5% of the nominal output from the DACs. For example, if the output current of the DAC is 4.33 mA, the DAC tune feature can change this output current from 4.008 mA (-7.5%) to 4.658 mA (+7.5%). The reset value of the vid_out_ctrl registers is 00h nominal DAC output current. The following table is an example of how the output current of the DACs varies for a nominal 4.33 mA output current.
300mV
Table XI.
NEGATIVE GAIN PROGRAMMED IN DAC OUTPUT LEVEL REGISTERS, SUBADDRESS 0Ah, 0Bh
CASE B
700mV
Reg 0Ah or 0Bh 0100 0000 (40h) 0011 1111 (3Fh) 0011 1110 (3Eh) ... ... 0000 0010 (02h) 0000 0001 (01h) 0000 0000 (00h)
Figure 40. Programmable DAC Gain--Positive and Negative Gain
DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 4.25 4.23 ... ... 4.018 4.013 4.008
% Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% -0.0180% -0.0360% ... ... -7.3640% -7.3820% -7.5000%
300mV
(I2C Reset Value, Nominal)
1111 1111 (FFh) 1111 1110 (FEh) ... ... 1100 0010 (C2h) 1100 0001 (C1h) 1100 0000 (C0h)
REV. A
-47-
ADV7310/ADV7311
Gamma Correction [Subaddress 24h-37h for HD, Subaddress 66h-79h for SD]
For example: y24 = [(8 / 224)0.5 x 224] + 16 = 58* y32 = [(16 / 224)0.5 x 224] + 16 = 76* y48 = [(32 / 224)0.5 x 224] + 16 = 101* y64 = [(48 / 224)0.5 x 224] + 16 =120* y80 = [(64 / 224)0.5 x 224] + 16 =136* y96 = [(80 / 224)0.5 x 224] + 16 = 150* y128 = [(112 / 224)0.5 x 224] + 16 = 174* y160 = [(144 / 224)0.5 x 224] + 16 = 195* y192 = [(176 / 224)0.5 x 224] + 16 = 214* y224 = [(208 / 224)0.5 x 224] + 16 = 232*
*rounded to the nearest integer
Gamma correction is available for SD and HD video. For each standard, there are twenty 8-bit wide registers. They are used to program the gamma correction curves A and B. HD gamma curve A is programmed at Addresses 24h to 2Dh, HD gamma curve B at 2Eh to 7h. SD gamma curve A is programmed at Addresses 66h to 6Fh, and SD gamma curve B at Addresses 70h to 79h. Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function SignalOUT = (Signal IN where = gamma power factor.
GAMMA CORRECTED AMPLITUDE
The gamma curves in Figures 46 and 47 are examples only; any user defined curve is acceptable in the range of 16 to 240.
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
)
Gamma correction is performed on the luma data only. The user may choose either of two different curves, curve A or curve B. At any one time, only one of these curves can be used. The response of the curve is programmed at 10 predefined locations. In changing the values at these locations, the gamma curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the 10 locations are at 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240, and 255 are fixed and cannot be changed. For the length of 16 to 240, the gamma correction curve has to be calculated as follows:
250 SIGNAL OUTPUT 200 0.5 150
100 SIGNAL INPUT 50
0
0
50
100
150 LOCATION
200
250
y = x
where: y = gamma corrected output x = linear input signal = gamma power factor
Figure 41. Signal Input (Ramp) and Signal Output for Gamma 0.5
GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
300
GAMMA CORRECTED AMPLITUDE
To program the gamma correction registers, the seven values for y have to be calculated using the following formula:
x( n -16) yn = (240 - 16) x (240 - 16) + 16
250 0.3 200 0.5 150
where: x(n - 16) = Value for x along x axis at points n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224 yn = Value for y along the y axis, which has to be written into the gamma correction register
100
G SI
N
AL
IN
PU
T
1.5
1.8
50
0
0
50
100
150 LOCATION
200
250
Figure 42. Signal Input (Ramp) and Selectable Output Curves
-48-
REV. A
ADV7310/ADV7311
HD SHARPNESS FILTER CONTROL AND ADAPTIVE FILTER CONTROL [Subaddress 20h, 38h-3Dh]
There are three filter modes available on the ADV7310/ADV7311: sharpness filter mode and two adaptive filter modes.
HD Sharpness Filter Mode
The derivative of the incoming signal is compared to the three programmable threshold values: HD adaptive filter threshold A, B, C. The recommended threshold range is from 16 to 235 although any value in the range of 0 to 255 can be used. The edges can then be attenuated with the settings in HD adaptive filter gain 1, 2, 3 registers and HD sharpness filter gain register. According to the settings of the HD adaptive filter mode control, there are two adaptive filter modes available: 1. Mode A is used when adaptive filter mode is set to 0. In this case, Filter B (LPF) will be used in the adaptive filter block. Also, only the programmed values for Gain B in the HD sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied when needed. The Gain A values are fixed and cannot be changed. 2. Mode B is used when adaptive filter mode is set to 1. In this mode, a cascade of Filter A and Filter B is used. Both settings for Gain A and Gain B in the HD sharpness filter gain, HD adaptive filter gain 1, 2, 3 become active when needed.
To enhance or attenuate the Y signal in the frequency ranges shown in the figures below, the following register settings must be used: HD sharpness filter must be enabled and HD adaptive filter enable must be set to disabled. To select one of the 256 individual responses, the according gain values for each filter, which range from -8 to +7, must be programmed into the HD sharpness filter gain register at Address 20h.
HD Adaptive Filter Mode
The HD adaptive filter threshold A, B, C registers, the HD adaptive filter gain 1, 2, 3 registers, and the HD sharpness gain register are used in adaptive filter mode. To activate the adaptive filter control, the HD sharpness filter must be enabled and HD adaptive filter enable must be enabled.
1.5 1.4 1.3 1.2
SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5 1.4 1.3 1.2
1.6
MAGNITUDE RESPONSE (Linear Scale)
1.5 1.4
MAGNITUDE
INPUT SIGNAL: STEP
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka)
MAGNITUDE
1.1 1.0 0.9 0.8 0.7 0.6 0.5 FREQUENCY (MHz) FILTER B RESPONSE (Gain Kb)
1.3
1.2
1.1
1.0
0
2
4 6 8 10 FREQUENCY (MHz)
12
FREQUENCY RESPONSE IN SHARPNESS FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 43. Sharpness and Adaptive Filter Control Block
REV. A
-49-
ADV7310/ADV7311
HD Sharpness Filter and Adaptive Filter Application Examples HD Sharpness Filter Application
The effect of the sharpness filter can also be seen when using the internally generated cross hatch pattern.
Table XIII.
The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the results shown in the figures below. Input data was generated by an external signal source.
Table XII.
Address 00h 01h 02h 10h 11h 20h
Register Setting FCh 10h 20h 00h 85h 99h
Address 00h 01h 02h 10h 11h 20h 20h 20h 20h 20h 20h
*See Figure 44.
Register Setting FCh 10h 20h 00h 81h 00h 08h 04h 40h 80h 22h
Reference*
a b c d e f
a
R2 1
d
b
R4 R1
e
c
f
1
R2
CH1 500mV REF A
500mV 4.00 s
M 4.00 s 1 9.99978ms
CH1 ALL FIELDS
CH1 500mV REF A
500mV 4.00 s
1
M 4.00 s 9.99978ms
CH1 ALL FIELDS
Figure 44. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value
-50-
REV. A
ADV7310/ADV7311
Adaptive Filter Control Application
Figures 45 and 46 show typical signals to be processed by the adaptive filter control block.
: 692mV @: 446mV : 332ns @: 12.8ms
When changing the adaptive filter mode to Mode B [Address 15h, Bit 6], the following output can be obtained:
: 674mV @: 446mV : 332ns @: 12.8ms
Figure 47. Output Signal from Adaptive Filter Control Figure 45. Input Signal to Adaptive Filter Control
: 692mV @: 446mV : 332ns @: 12.8ms
The adaptive filter control can also be demonstrated using the internally generated cross hatch test pattern and toggling the adaptive filter control bit [Address 15h, Bit 7].
Table XV.
Address 00h 01h 02h 10h 11h 15h 20h 38h 39h 3Ah 3Bh 3Ch 3Dh
Register Setting FCh 38h 20h 00h 85h 80h 00h ACh 9Ah 88h 28h 3Fh 64h
Figure 46. Output Signal after Adaptive Filter Control
The following register settings were used to obtain the results shown in Figure 46, i.e., to remove the ringing on the Y signal. Input data was generated by an external signal source.
Table XIV.
Address 00h 01h 02h 10h 11h 15h 20h 38h 39h 3Ah 3Bh 3Ch 3Dh
Register Setting FCh 38h 20h 00h 81h 80h 00h ACh 9Ah 88h 28h 3Fh 64h
All other registers are set as normal/default.
REV. A
-51-
ADV7310/ADV7311
SD Digital Noise Reduction [Subaddress 63h, 64h, 65h]
DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER
DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal [DNR input select]. The absolute value of the filter output is compared to a programmable threshold value ['DNR threshold control]. There are two DNR modes available: DNR mode and DNR sharpness mode. In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount [coring gain border, coring gain data] of this noise signal will be subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal [coring gain border, coring gain data] will be added to the original signal in order to boost high frequency components and sharpen the video image. In MPEG systems, it is common to process the video information in blocks of 8 pixels x 8 pixels for MPEG2 systems, or 16 pixels x 16 pixels for MPEG1 systems [block size control]. DNR can be applied to the resulting block transition areas that are known to contain noise. Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels [border area]. It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the [DNR block offset]. The digital noise reduction registers are three 8-bit registers. They are used to control the DNR processing.
Y DATA INPUT
INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? - + DNR OUT MAIN SIGNAL PATH SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL
Y DATA INPUT
FILTER OUTPUT > THRESHOLD
DNR SHARPNESS MODE
DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN
NOISE SIGNAL PATH
CORING GAIN DATA CORING GAIN BORDER
INPUT FILTER BLOCK FILTER OUTPUT > THRESHOLD? + + DNR OUT ADD SIGNAL ABOVE THRESHOLD RANGE FROM ORIGINAL SIGNAL
FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH
Figure 48. DNR Block Diagram
-52-
REV. A
ADV7310/ADV7311
Coring Gain Border [Address 63h, Bits 3-0] Block Size Control [Address 64h, Bit 7]
These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.
Coring Gain Data [Address 63h, Bits 7-4]
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic 1 defines a 16 pixel x 16 pixel data block, and a Logic 0 defines an 8 pixel x 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.
DNR Input Select Control [Address 65h, Bit 2-0]
Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that will be DNR processed. Figure 51 shows the filter responses selectable with this control.
1.0 FILTER D 0.8
These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block.
MAGNITUDE
In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output, which lies below the set threshold range. The result is then subtracted from the original signal. In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.
APPLY DATA CORING GAIN APPLY BORDER CORING GAIN
FILTER C 0.6
0.4
FILTER B
0.2 FILTER A 0
0
1
2
3 4 FREQUENCY (Hz)
5
6
OXXXXXXOOXXXXXXO OFFSET CAUSED BY VARIATIONS IN INPUT TIMING
Figure 51. DNR Input Select
DNR Mode Control [Address 65h, Bit 4]
OXXXXXXOOXXXXXXO
DNR27 - DNR24 = 01h
OXXXXXXOOXXXXXXO
This bit controls the DNR mode selected. A Logic 0 selects DNR mode; a Logic 1 selects DNR sharpness mode. DNR works on the principle of defining low amplitude, high frequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal that lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR sharpness mode is enabled, it is possible to add a fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal will be boosted (similar to using Extended SSAF filter).
Block Offset Control [Address 65h, Bits 7-4]
Figure 49. DNR Offset Control
DNR Threshold [Address 64h, Bits 5-0]
These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.
Border Area [Address 64h, Bit 6]
When this bit is set to a Logic 1, the block transition area can be defined to consist of four pixels. If this bit is set to a Logic 0, the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.
720 485 PIXELS (NTSC) 2-PIXEL BORDER DATA
Four bits are assigned to this control, which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
8 8 PIXEL BLOCK
8 8 PIXEL BLOCK
Figure 50. DNR Border Area
REV. A
-53-
ADV7310/ADV7311
SD ACTIVE VIDEO EDGE [Subaddress 42h, Bit 7] SAV/EAV Step Edge Control
When the active video edge is enabled, the first three pixels and the last three pixels of the active video on the luma channel are scaled in such a way that maximum transitions on these pixels are not possible. The scaling factors are x1/8, x1/2, and x 7/8. All other active video passes through unprocessed.
The ADV7310/ADV7311 has the capability of controlling fast rising and falling signals at the start and end of active video to minimize ringing. An algorithm monitors SAV and EAV and governs when the edges are too fast. The result will be reduced ringing at the start and end of active video for fast transitions. Subaddress 0x42, Bit 7 = 1 enables this feature.
LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 12.5 IRE 0 IRE
LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED
Figure 52. Example of Active Video Edge Functionality
VOLTS IRE:FLT
100
0.5
50
0
0
-50 0 2 4 6
F2 L135 8 10 12
Figure 53. Address 0x42, Bit 7 = 0
VOLTS IRE:FLT
100
0.5
50
0
0
-50 -2 0 2 4
F2 L135 6 8 10 12
Figure 54. Address 0x42, Bit 7 = 1
-54-
REV. A
ADV7310/ADV7311
BOARD DESIGN AND LAYOUT CONSIDERATIONS DAC Termination and Layout Considerations
10 H DAC OUTPUT 600 22pF 600 4 560 560 3 75 1 BNC OUTPUT
The ADV7310/ADV7311 contain an on-board voltage reference. The ADV7310/ADV7311 can be used with an external VREF (AD1580). The RSET resistors are connected between the RSET pins and AGND and are used to control the full-scale output current and therefore the DAC voltage output levels. For full-scale output, RSET must have a value of 3040 . The RSET values should not be changed. RLOAD has a value of 300 for full-scale output.
Video Output Buffer and Optional Output Filter
Figure 55. Example of Output Filter for SD, 16x Oversampling
0 -10 MAGNITUDE (dB) -20 -30
GAIN (dB)
CIRCUIT FREQUENCY RESPONSE
0 24n -30 21n -60 18n -90 15n -120
Output buffering on all six DACs is necessary in order to drive output devices, such as SD or HD monitors. Analog Devices produces a range of suitable op amps for this application, for example the AD8061. More information on line driver buffering circuits is given in the relevant op amps' data sheets. An optional analog reconstruction low-pass filter (LPF) may be required as an anti-imaging filter if the ADV7310/ADV7311 is connected to a device that requires this filtering. The filter specifications vary with the application.
Table XVI. External Filter Requirements
-40 PHASE (Deg) -50 GROUP DELAY (sec) -60 -70 -80 1M
12n -150 9n -180 6n -210 3n -240 0 1G
Cutoff Frequency Attenuation Application Oversampling (MHz) -50 dB @ (MHz) SD SD PS PS HDTV HDTV 2x 16x 1x 8x 1x 2x >6.5 >6.5 >12.5 >12.5 >30 >30 20.5 209.5 14.5 203.5 44.25 118.5
10M 100M FREQUENCY (Hz)
Figure 56. Filter Plot for Output Filter for SD, 16x Oversampling
REV. A
-55-
ADV7310/ADV7311
4.7 H DAC OUTPUT 6.8pF 600 6.8pF 600 4 560 GAIN (dB) 560 3 75 1 BNC OUTPUT
0 -10 MAGNITUDE (dB) -20 -30 -40 -50 -60 -70 GROUP DELAY (Sec) 320 14n 240 PHASE (Deg) 160 80 8n 0 6n -80 4n -160 2n -240 0 1G 12n 10n
CIRCUIT FREQUENCY RESPONSE
480 18n 400 16n
Figure 57. Example of Output Filter for PS, 8x Oversampling
DAC OUTPUT 3 300 4 1 75 470nH 220nH 3 33pF 82pF 75 4 500 500 1 BNC OUTPUT
-80 -90 1M
10M 100M FREQUENCY (Hz)
Figure 59. Filter Plot for Output Filter for PS, 8x Oversampling
0
CIRCUIT FREQUENCY RESPONSE
480 18n
Figure 58. Example of Output Filter for HDTV, 2x Oversampling
Table XVII. Possible Output Rates From the ADV7310/ADV7311
-10
MAGNITUDE (dB)
360 15n 240
-20
GAIN (dB)
Input Mode Address 01h, Bit 6-4 SD Only PS Only HDTV Only
PLL Address 00h, Bit 1 Off On Off On Off On
Output Rate (MHz) 27 (2x) 216 (16x) 27 (1x) 216 (8x) 74.25 (1x) 148.5 (2x)
GROUP DELAY (sec) -30 120
12n
9n 0 6n PHASE (Deg) -120 3n -240 0
-40
-50
-60 1M
10M 100M FREQUENCY (Hz)
1G
Figure 60. Filter Plot for Output Filter for HDTV, 2x Oversampling
-56-
REV. A
ADV7310/ADV7311
PCB Board Layout Considerations Supply Decoupling
The ADV7310/ADV7311 are optimally designed for lowest noise performance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7310/ADV7311, it is imperative that great care be given to the PC board layout. The layout should be optimized for lowest noise on the ADV7310/ ADV7311 power and ground lines. This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and AGND, VDD and DGND, and VDD_IO and GND_IO pins should be kept as short as possible to minimized inductive ringing. It is recommended that a 4-layer printed circuit board is used, with power and ground planes separating the layer of the signal carrying traces of the components and solder side layer. Component placement should be carefully considered in order to separate noisy circuits, such as crystal clocks, high speed logic circuitry, and analog circuitry. There should be a separate analog ground plane and a separate digital ground plane. Power planes should encompass a digital power plane and an analog power plane. The analog power plane should contain the DACs and all associated circuitry, VREF circuitry. The digital power plane should contain all logic circuitry. The analog and digital power planes should be individually connected to the common power plane at a single point through a suitable filtering device, such as a ferrite bead. DAC output traces on a PCB should be treated as transmission lines. It is recommended that the DACs be placed as close as possible to the output connector, with the analog output traces being as short as possible (less than 3 inches). The DAC termination resistors should be placed as close as possible to the DAC outputs and should overlay the PCB's ground plane. As well as minimizing reflections, short analog output traces will reduce noise pickup due to neighboring digital circuitry. To avoid crosstalk between the DAC outputs, it is recommended that as much space as possible be left between the tracks of the individual DAC output pins. The addition of ground tracks between outputs is also recommended.
Noise on the analog power plane can be further reduced by the use of decoupling capacitors. Optimum performance is achieved by the use of 10 nF and 0.1 F ceramic capacitors. Each group of VAA, VDD, or VDD_IO pins should be individually decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. A 1 F tantalum capacitor is recommended across the VAA supply in addition to 10 nF ceramic. See the circuit layout in Figure 61.
Digital Signal Interconnect
The digital signal lines should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7310/ADV7311 should be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the digital power plane and not the analog power plane.
Analog Signal Interconnect
The ADV7310/ADV7311 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. For optimum performance, the analog outputs should each be source and load terminated, as shown in Figure 61. The termination resistors should be as close as possible to the ADV7310/ADV7311 to minimize reflections. For optimum performance, it is recommended that all decoupling and external components relating to the ADV7310/ADV7311 be located on the same side of the PCB and as close as possible to the ADV7310/ADV7311. Any unused inputs should be tied to ground.
REV. A
-57-
ADV7310/ADV7311
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP VAA VAA 0.1 F VDD_IO 10, 56 5k
45 36 41 1
+ 10nF 0.1 F 10nF 0.1 F 1F
VAA
VDD
VDD_IO 10nF 0.1 F 1.1k
VAA
COMP1, 2
19 I2C
VAA
VDD VDD_IO VREF 46 100nF DAC A 44 300 DAC B 43 300 DAC C 42 300 DAC D 39 300
ADV7310/ ADV7311
S0-S9
50 S_HSYNC 49 S_VSYNC 48 S_BLANK
RECOMMENDED EXTERNAL AD1580 FOR OPTIMUM PERFORMANCE
UNUSED INPUTS SHOULD BE GROUNDED
C0-C9
Y0-Y9
63 CLKIN_B 23 P_HSYNC
DAC E 38 300 DAC F 37 300 100 100 VDD_IO 5k 3040 RSET1 47 3040 SELECTION HERE DETERMINES DEVICE ADDRESS VDD_IO 5k VDD_IO 5k I2C BUS
VAA 4.7k +
24 P_VSYNC 25 P_BLANK 33 RESET
4.7 F
32 CLKIN_A
SCLK 22 SDA 21
VAA
820pF
34 EXT_LF
ALSB 20 RSET2 35
680
3.9nF
GND_ IO
64
AGND DGND
40
11, 57
Figure 61. ADV7310/ADV7311 Circuit Layout
-58-
REV. A
ADV7310/ADV7311
APPENDIX 1--COPY GENERATION MANAGEMENT SYSTEM PS CGMS Data Registers 2-0 [Subaddress 21h, 22h, 23h] 1080i System
CGMS data is applied to Line 19 and on Line 582 of the luminance vertical blanking interval.
CGMS Functionality
PS CGMS is available in 525p mode conforming to CGMS-A EIA-J CPR1204-1, transfer method of video ID information using vertical blanking interval (525p system), March 1998, and IEC61880, 1998, Video systems (525/60)--video and accompanied data using the vertical blanking interval--analog interface. When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1], CGMS data is inserted on line 41. The PS CGMS data registers are at Addresses 21h, 22h, and 23h.
SD CGMS Data Registers 2-0 [Subaddress 59h, 5Ah, 5Bh]
The ADV7310/ADV7311 supports Copy Generation Management System (CGMS), conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on odd and even fields. CGMS data can be transmitted only when the ADV7310/ADV7311 is configured in NTSC mode. The CGMS data is 20 bits long, and the function of each of these bits is as shown in the following table. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit; see Figure 63.
HD/PS CGMS [Address 12h, Bit 6]
If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits, C19-C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7310/ADV7311 based on the lower 14 bits (C0-C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial x6 + x + 1 with a preset value of 111111. If SD CGMS CRC [Address 59h, Bit 4] and PS/HD CGMS CRC [Address 12h, Bit 7] is set to a Logic 0, all 20 bits (C0-C19) are output directly from the CGMS registers (no CRC is calculated, must be calculated by the user).
Table XVIII.
Bit WORD0 B1 B2 B3 WORD0 B4, B5, B6 WORD1 B7, B8, B9, B10 WORD2 B11, B12, B13, B14
Function Aspect ratio Display format Undefined 1 16:9 Letterbox 0 4:3 Normal
The ADV7310/ADV7311 supports Copy Generation Management System (CGMS) in HDTV mode (720p and 1080i) in accordance with EIAJ CPR-1204-2. The HD CGMS data registers are to be found at address 021h, 22h, 23h.
Function of CGMS Bits
Identification information about video and other signals (e.g., audio) Identification signal incidental to Word 0 Identification signal and information incidental to Word 0
Word 0-6 bits; Word 1-4 bits; Word 2-6 bits; CRC 6 bits CRC polynomial = x6 + x + 1 (preset to 111111)
720p System
CGMS data is applied to Line 24 of the luminance vertical blanking interval.
REV. A
-59-
ADV7310/ADV7311
CRC SEQUENCE +700mV REF 70% 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV -300mV 5.8 s 0.15 s 6T BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
21.2 s 0.22 s 22T T = 1/(fH 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T 30ns
Figure 62. Progressive Scan CGMS Waveform
+100 IRE REF +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE -40 IRE 11.2 s 2.235 s 20ns CRC SEQUENCE
49.1 s
0.5 s
Figure 63. Standard Definition CGMS Waveform Diagram
+700mV REF 70% 10%
CRC SEQUENCE BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV T -300mV 4T 3.128 s 90ns 30ns 17.2 s 160ns 22 T
T = 1/(fH 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 64. HDTV 720p CGMS Waveform
+700mV REF 70% 10%
CRC SEQUENCE BIT1 BIT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT20
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV T -300mV 4T 4.15 s 60ns 30ns 22.84 s 210ns 22 T
T = 1/(fH 2200/77) = 1.038 s fH = HORIZONTAL SCAN FREQUENCY
1H
Figure 65. HDTV 1080i CGMS Waveform
-60-
REV. A
ADV7310/ADV7311
APPENDIX 2--SD WIDE SCREEN SIGNALING [Subaddress 59h, 5Ah, 5Bh]
The ADV7310/ADV7311 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in PAL mode. The WSS data is 14 bits long, and the function of each of these bits is shown in Table XIX. The WSS data is
preceded by a run-in sequence and a start code; see Figure 66. If SD WSS [Address 59h, Bit 7] is set to a Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s from the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 61h, Bit 7.
Table XIX. Function of WSS Bits
Bit Bit 0-Bit 2 Bit 3 B0, 0 1 0 1 0 1 0 1 1 B4 0 1 B1, 0 0 1 1 0 0 1 1 1 B2, 0 0 0 0 1 1 1 1 1 B3 1 0 0 1 0 1 1 0 0
Description Aspect Ratio/Format/Position Odd Parity Check of Bit 0 to Bit 2 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 16:9 Camera Mode Film Mode Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format N/A Position N/A Center Top Center Top Center Center N/A
Bit B5 0 1 B6 0 1 B7 B9 0 1 0 1 B11 0 1 B12 B13 B10 0 0 1 1
Description Standard Coding Motion Adaptive Color Plus No Helper Modulated Helper Reserved No Open Subtitles Subtitles in Active Image Area Subtitles out of Active Image Area Reserved No Surround Sound Information Surround Sound Mode Reserved Reserved
500mV RUN-IN SEQUENCE START CODE
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
ACTIVE VIDEO
11.0 s 38.4 s 42.5 s
Figure 66. WSS Waveform Diagram
REV. A
-61-
ADV7310/ADV7311
APPENDIX 3--SD CLOSED CAPTIONING [Subaddress 51h-54h]
ADV7311. All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled. FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7310/ADV7311 use a single buffering method. This means that the closed captioning buffer is only 1-byte deep; therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is output on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (two bytes) in every field. If no new data is required for transmission, 0s must be inserted in both data registers; this is called nulling. It is also important to load control codes, all of which are double bytes on Line 21, or a TV will not recognize them. If there is a message like "Hello World" that has an odd number of characters, it is important to pad it out to even in order to get "end of caption" 2-byte control code to land in the same field.
The ADV7310/ADV7311 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic 1 start bit. Sixteen bits of data follow the start bit. These consist of two 8-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in the SD closed captioning registers [Address 53h-54h]. The ADV7310/ADV7311 also support the extended closed captioning operation, which is active during even fields and is encoded on Scan Line 284. The data for this operation is stored in the SD closed captioning registers [Address 51h-52h]. All clock run-in signals and timing to support closed captioning on Lines 21 and 284 are generated automatically by the ADV7310/
10.5
0.25 s
12.91 s 7 CYCLES OF 0.5035MHz CLOCK RUN-IN TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) S T A R T P A R I T Y P A R I T Y
50 IRE
D0-D6
D0-D6
BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s
BYTE 1
33.764 s
Figure 67. Closed Captioning Waveform, NTSC
-62-
REV. A
ADV7310/ADV7311
APPENDIX 4--TEST PATTERNS
The ADV7310/ADV7311 can generate SD and HD test patterns.
T
T
2
2
CH2 200mV
M 10.0 s A CH2 30.6000 s T
1.20V
CH2 100mV
M 10.0 s CH2 1.82600ms T
EVEN
Figure 68. NTSC Color Bars
Figure 71. PAL Black Bar [-21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV]
T
T
2
2
CH2 200mV
M 10.0 s A CH2 30.6000 s T
1.21V
CH2 200mV
M 4.0 s CH2 1.82944ms T
EVEN
Figure 69. PAL Color Bars
Figure 72. 525p Hatch Pattern
T
T
2
2
CH2 100mV
M 10.0 s CH2 1.82380ms T
EVEN
CH2 200mV
M 4.0 s CH2 1.84208ms T
EVEN
Figure 70. NTSC Black Bar [-21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV]
Figure 73. 625p Hatch Pattern
REV. A
-63-
ADV7310/ADV7311
T T
2 2
CH2 200mV
M 4.0 s CH2 1.82872ms T
EVEN
CH2 100mV
M 4.0 s CH2 1.82936ms T
EVEN
Figure 74. 525p Field Pattern
Figure 76. 525p Black Bar [-35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV]
T
T
2 2
CH2 200mV
M 4.0 s CH2 1.84176ms T
EVEN
CH2 100mV
M 4.0 s CH2 1.84176ms T
EVEN
Figure 75. 625p Field Pattern
Figure 77. 625p Black Bar [-35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV]
-64-
REV. A
ADV7310/ADV7311
The following register settings are used to generate an SD NTSC CVBS output on DAC A: Register Setting 80h 10h 40h 40h 08h For PAL black bar pattern output on DAC A, the same settings are used except that subaddress = 40h and register setting = 11h. The following register settings are used to generate a 525p hatch pattern on DAC D: Register Setting 10h 10h 40h 05h A0h 80h 80h
Subaddress 00h 40h 42h 44h 4Ah
Subaddress 00h 01h 10h 11h 16h 17h 18h
All other registers are set as normal/default.
For PAL CVBS output on DAC A, the same settings are used except that subaddress = 40h and register setting = 11h. The following register settings are used to generate an SD NTSC black bar pattern output on DAC A: Register Setting 80h 04h 10h 40h 40h 08h
All other registers are set as normal/default.
For 625p hatch pattern on DAC D, the same register settings are used except that subaddress = 10h and register setting = 50h. For a 525p black bar pattern output on DAC D, the same settings are used as above except that subaddress = 02h and register setting = 24h. For 625p black bar pattern output on DAC D, the same settings are used as above except that subaddress = 02h and register setting = 24h; and subaddress = 10h and register setting = 50h.
Subaddress 00h 02h 40h 42h 44h 4Ah
All other registers are set as normal/default.
REV. A
-65-
ADV7310/ADV7311
APPENDIX 5--SD TIMING MODES [Subaddress 4Ah] Mode 0 (CCIR-656)--Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7310/ADV7311 is controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. S_VSYNC, S_HSYNC, and S_BLANK (if not used) pins should be tied high during this mode. Blank output is available.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F0 0X818 1 Y Y r F0 0Y000 0 0FFAAA 0FFBBB ANCILLARY DATA (HANC) 268 CLOCK 4 CLOCK PAL SYSTEM (625 LINES/50Hz) 280 CLOCK END OF ACTIVE VIDEO LINE
SAV CODE C C 8 1 8 1 F 0 0X CY C YC Y rYb b 0000F00Yb r
4 CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz)
4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE
Figure 78. SD Slave Mode 0
-66-
REV. A
ADV7310/ADV7311
Mode 0 (CCIR-656)--Master Option (Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7310/ADV7311 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H bit is output on the S_HSYNC, the V bit is output on S_BLANK, and the F bit is output on S_VSYNC.
DISPLAY VERTICAL BLANK
DISPLAY
522 H
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
V
F
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260 H
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
V
F
ODD FIELD
EVEN FIELD
Figure 79. SD Master Mode 0, NTSC
DISPLAY VERTICAL BLANK DISPLAY
622 H V
623
624
625
1
2
3
4
5
6
7
21
22
23
F
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309 H
310
311
312
313
314
315
316
317
318
319
320
334
335
336
V F ODD FIELD EVEN FIELD
Figure 80. SD Master Mode 0, PAL
REV. A
-67-
ADV7310/ADV7311
ANALOG VIDEO
H
F
V
Figure 81. SD Master Mode 0, Data Transitions
Mode 1--Slave Option (Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7310/ADV7311 accept horizontal sync and odd/even field signals. A transition of the field input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624. HSYNC is input on S_HSYNC, BLANK on S_BLANK, and FIELD on S_VSYNC.
DISPLAY VERTICAL BLANK
DISPLAY
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 82. SD Slave Mode 1 (NTSC)
-68-
REV. A
ADV7310/ADV7311
Mode 1--Master Option (Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7310/ADV7311 can generate horizontal sync and odd/even field signals. A transition of the field input when HSYNC is low indicates a new frame, i.e., vertical retrace. The blank signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC is output on the S_HSYNC, BLANK on S_BLANK, and FIELD on S_VSYNC.
DISPLAY
DISPLAY VERTICAL BLANK
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 83. SD Slave Mode 1 (PAL)
HSYNC
FIELD
PAL = 12 NTSC = 16 BLANK
CLOCK/2 CLOCK/2
PIXEL DATA
Cb
Y
Cr
Y
PAL = 132 NTSC = 122
CLOCK/2 CLOCK/2
Figure 84. SD Timing Mode 1--Odd/Even Field Transitions Master/Slave
REV. A
-69-
ADV7310/ADV7311
Mode 2-- Slave Option (Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7310/ADV7311 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624. HSYNC is input S_HSYNC, BLANK on S_BLANK, and VSYNC on S_VSYNC.
DISPLAY
VERTICAL BLANK
DISPLAY
522 HSYNC BLANK VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD DISPLAY
ODD FIELD DISPLAY VERTICAL BLANK
260 HSYNC BLANK VSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 85. SD Slave Mode 2 (NTSC)
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC BLANK VSYNC
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK VSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 86. SD Slave Mode 2 (PAL)
-70-
REV. A
ADV7310/ADV7311
Mode 2--Master Option (Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7310/ADV7311 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624. HSYNC is output on S_HSYNC , BLANK on S_BLANK, and VSYNC on S_VSYNC.
HSYNC
VSYNC
BLANK
PAL = 12 NTSC = 16
CLOCK/2 CLOCK/2
PIXEL DATA PAL = 132 NTSC = 122 CLOCK/2 CLOCK/2
Cb
Y
Cr
Y
Figure 87. SD Timing Mode 2 Even to Odd Field Transition Master/Slave
HSYNC
VSYNC PAL = 12 NTSC = 16 BLANK CLOCK/2 CLOCK/2 PAL = 864 NTSC = 858 CLOCK/2 CLOCK/2
PIXEL DATA
Cb
Y
Cr
Y
Cb
PAL = 132 NTSC = 122
CLOCK/2 CLOCK/2
Figure 88. SD Timing Mode 2 Odd to Even Field Transition Master/Slave
REV. A
-71-
ADV7310/ADV7311
Mode 3--Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7310/ADV7311 accept or generate horizontal sync and odd/even field signals. A transition of the field input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7310/ADV7311 automatically blank all normally blank lines as per CCIR-624. HSYNC is output in master mode and input in slave mode on S_VSYNC, BLANK on S_BLANK, and VSYNC on S_VSYNC.
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
VERTICAL BLANK
DISPLAY
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 89. SD Timing Mode 3 (NTSC)
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
EVEN FIELD
ODD FIELD
Figure 90. SD Timing Mode 3 (PAL)
-72-
REV. A
ADV7310/ADV7311
APPENDIX 6--HD TIMING
DISPLAY
FIELD 1
VERTICAL BLANKING INTERVAL
1124 P_VSYNC
1125
1
2
3
4
5
6
7
8
20
21
22
560
P_HSYNC
DISPLAY
FIELD 2
VERTICAL BLANKING INTERVAL
561 P_VSYNC
562
563
564
565
566
567
568
569
570
583
584
585
1123
P_HSYNC
Figure 91. 1080i HSYNC and VSYNC Input Timing
REV. A
-73-
ADV7310/ADV7311
APPENDIX 7--VIDEO OUTPUT LEVELS HD YPrPb Output Levels
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
940
940
700mV 700mV
64 300mV
64 300mV
EIA-770.2, STANDARD FOR Pr/Pb 960
EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960
OUTPUT VOLTAGE
600mV 512 512 700mV 700mV
64 64
Figure 92. EIA 770.2 Standard Output Signals (525p/625p)
INPUT CODE EIA-770.1, STANDARD FOR Y OUTPUT VOLTAGE 782mV
Figure 94. EIA 770.3 Standard Output Signals (1080i, 720p)
INPUT CODE 1023 Y-OUTPUT LEVELS FOR FULL INPUT SELECTION OUTPUT VOLTAGE
940
700mV
714mV
64
64 286mV
300mV
INPUT CODE
EIA-770.1, STANDARD FOR Pr/Pb 960 OUTPUT VOLTAGE
Pr/Pb-OUTPUT LEVELS FOR FULL INPUT SELECTION
OUTPUT VOLTAGE
1023
700mV
512 700mV
64 300mV
64
Figure 93. EIA 770.1 Standard Output Signals (525p/625p)
Figure 95. Output Levels for Full Input Selection
-74-
REV. A
ADV7310/ADV7311
RGB Output Levels
700mV
550mV
700mV
550mV
300mV
300mV
700mV
550mV
700mV
550mV
300mV
300mV
700mV
550mV
700mV
550mV
300mV
300mV
Figure 96. HD RGB Output Levels
Figure 98. SD RGB Output Levels--RGB Sync Disabled
700mV
550mV
700mV
550mV
300mV
300mV
0mV
0mV
700mV
550mV
700mV
550mV
300mV
300mV
0mV
0mV
700mV
550mV
700mV
550mV
300mV
300mV
0mV
0mV
Figure 97. HD RGB Output Levels--RGB Sync Enabled
Figure 99. SD RGB Output Levels--RGB Sync Enabled
REV. A
-75-
ADV7310/ADV7311
YUV Output Levels
MAGENTA
YELLOW
GREEN
MAGENTA
BLACK
WHiTE
CYAN
YELLOW
BLUE
RED
GREEN
332mV 280mV 220mV
2150mV 200mV
1260mV 1000mV
160mV
900mV
110mV 60mV
140mV
Figure 100. U Levels--NTSC
MAGENTA YELLOW GREEN BLACK
Figure 103. U Levels--PAL
WHITE
CYAN
BLUE
RED
GREEN
280mV 220mV
160mV
110mV 60mV
300mV
Figure 101. U Levels--PAL
MAGENTA YELLOW GREEN BLACK
Figure 104. Y Levels--NTSC
WHITE
CYAN
BLUE
MAGENTA
RED
YELLOW
GREEN
2150mV 200mV
1260mV 1000mV 900mV
300mV
140mV
Figure 102. U Levels--NTSC
Figure 105. Y Levels--PAL
-76-
BLACK
WHITE
CYAN
BLUE
RED
BLACK
WHITE
CYAN
BLUE
332mV
MAGENTA
YELLOW
RED
BLACK
WHITE
CYAN
BLUE
RED
REV. A
ADV7310/ADV7311
VOLTS IRE:FLT
100
0.5 50
0
0
-50
F1 L76 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = A FRAMES SELECTED 1 2
0
10
APL = 44.5% 525 LINE NTSC SLOW CLAMP TO 0.00V AT 6.72 s
Figure 106. NTSC Color Bars 75%
VOLTS 0.4
IRE:FLT 50
0.2
0
0
-0.2
-50 -0.4 F1 L76 0 10 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED 1 2
NOISE REDUCTION: 15.05dB APL NEEDS SYNC-SOURCE. 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s
Figure 107. NTSC Chroma
REV. A
-77-
ADV7310/ADV7311
VOLTS 0.6 IRE:FLT
0.4 50 0 0.2
0
0
-0.2 F2 L238 10 NOISE REDUCTION: 15.05dB APL = 44.3% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 1 2
Figure 108. NTSC Luma
VOLTS 0.6
0.4
0.2
0
-0.2 L608 0 10 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1 2 3 4
NOISE REDUCTION: 0.00dB APL = 39.1% 625 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s
Figure 109. PAL Color Bars 75%
-78-
REV. A
ADV7310/ADV7311
VOLTS 0.5
0
-0.5 L575 10 APL NEEDS SYNC-SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s 20 30 40 50 60 MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1
Figure 110. PAL Chroma
VOLTS
0.5
0
L575 0 10 20 30 40 50 60 70 MICROSECONDS NO BUNCH SIGNAL PRECISION MODE OFF SYNCHRONOUS SOUND-IN-SYNC OFF FRAMES SELECTED 1
APL NEEDS SYNC-SOURCE. 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 AT 6.72 s
Figure 111. PAL Luma
REV. A
-79-
ADV7310/ADV7311
APPENDIX 8--VIDEO STANDARDS
0HDATUM SMPTE 274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING *1 4T EAV CODE 272T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T SAV CODE 1920T DIGITAL ACTIVE LINE C Y r
INPUT PIXELS
F F
0 0
0F 0V H*
F0 F0
C 0F C 0V b Y r H*
4 CLOCK 0 2199
4 CLOCK
SAMPLE NUMBER
2112
2116 2156
44
188
192
2111
FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1-562: F = 0 SAV/EAV: LINE 563-1125: F = 1 SAV/EAV: LINE 1-20; 561-583; 1124-1125: V = 1 SAV/EAV: LINE 21-560; 584-1123: V = 0 FOR A FIELD RATE OF 30Hz: 40 SAMPLES FOR A FIELD RATE OF 25Hz: 480 SAMPLES
Figure 112. EAV/SAV Input Data Timing Diagram--SMPTE 274M
SMPTE 293M
ANALOG WAVEFORM
EAV CODE F V H*
ANCILLARY DATA (OPTIONAL) F F
SAV CODE F 0 V 0 H*
DIGITAL ACTIVE LINE C C bYr C Yr Y
INPUT PIXELS
F F
0 0
0 0
0 0
4 CLOCK SAMPLE NUMBER 719 723 736 0HDATUM 799 853
4 CLOCK 857 0 719
DIGITAL HORIZONTAL BLANKING FVH* = FVH AND PARITY BITS SAV: LINE 43-525 = 200H SAV: LINE 1-42 = 2AC EAV: LINE 43-525 = 274H EAV: LINE 1-42 = 2D8
Figure 113. EAV/SAV Input Data Timing Diagram--SMPTE 293M
-80-
REV. A
ADV7310/ADV7311
ACTIVE VIDEO VERTICAL BLANK ACTIVE VIDEO
522
523
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 114. SMPTE 293M (525p)
ACTIVE VIDEO ACTIVE VIDEO
VERTICAL BLANK
622
623
624
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 115. ITU-R BT.1358 (625p)
DISPLAY VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
25
26
27
744
745
Figure 116. SMPTE 296M (720p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
583
584
585
1123
Figure 117. SMPTE 274M (1080i)
REV. A
-81-
ADV7310/ADV7311
OUTLINE DIMENSIONS 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64)
Dimensions shown in millimeters
0.75 0.60 0.45 SEATING PLANE
1.60 MAX
1
12.00 BSC SQ
64 49 48
PIN 1
TOP VIEW
(PINS DOWN)
10.00 BSC SQ
1.45 1.40 1.35
10 6 2
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
16 17 32 33
0.15 0.05
SEATING PLANE
VIEW A
ROTATED 90 CCW
0.50 BSC
0.27 0.22 0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
-82-
REV. A
ADV7310/ADV7311 Revision History
Location 8/03--Data Sheet changed from REV. 0 to REV. A. Page
Addition to Standards Directly Supported Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to Figure 13 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Change to Table XI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Updated Figure 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Updated Figures 59 and 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Change to Figure 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Deletion of line from notes in Figure 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
REV. A
-83-
-84-
C03748-0-8/03(A)

▲Up To Search▲

Price & Availability of ADV7310

	To Download ADV7310 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .